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Intelligent Integration

As system designers, we encounter the integration question at a much lower level. Processors, peripherals, memory, interconnect, and storage are all basic components of almost every modern electronic system design. A successful system designer has to balance the forces of form factor, power, price, performance, reliability, security, scalability, and product evolution in order to make the crucial decision of what and how to integrate, and what to leave discrete. While there are myriad options available, there is no reliable formula or roadmap to guide us through this complex engineering tradeoff.

As system designers, the first thing we … Read More → "Intelligent Integration"

Second Annual FPGA Journal Awards

Last year, with little fanfare, we presented our first annual FPGA Journal Reader’s choice awards. The response was fantastic, and everybody wanted to know how they could participate in this year’s awards process… It doesn’t work that way, of course. We use a super-secret balloting system and carefully guard the data to prevent any unscrupulous parties from tampering with the results.

This year, over 350 design teams answered our call to rate their experience with FPGA and EDA companies’ products and services. Each customer was required to answer based on … Read More → "Second Annual FPGA Journal Awards"

FPGA Journal Turns Two

It’s time again to bring home that cake from the grocery store bakery, ditch the box, mess around with the frosting a bit so it looks more “homemade,” and tell the guests that you spent all afternoon baking it. FPGA Journal is turning 24 months old (that’s 11000 for those of you that absolutely can’t let go of binary math, even for a party). Since October 1, 2003, we’ve brought you hundreds of feature articles, thousands of press releases, a good number of controversies, and 104 weekly e-mail newsletters.

This week, in … Read More → "FPGA Journal Turns Two"

Rationalizing Reconfigurability

About twenty years ago, there were two well-known approaches to custom IC implementation. The first, which we called “Full Custom,” was the high-end methodology. Polygons were painstakingly pushed across Calma screens by determined designers working to eek out every ounce of performance from fiery five-micron silicon technology. Full Custom design was difficult and expensive – not for the faint of heart or the financially challenged.

The second option at that time was Gate Array. Gate Array was for product teams with deadlines to meet and more important things to do than fighting with design rule … Read More → "Rationalizing Reconfigurability"

Allan Cantle

Allan Cantle knows what it takes to design high-performance digital systems. He’s been proving it since his early days at BAE Systems, where he was creating real-time simulations of evasive enemy targets to be used with real-world missiles in targeting practice. Allan has always had a knack for decomposing a complex problem into manageable-sized chunks, then mapping those chunks onto the appropriate architectures with the right interconnect to hit aggressive performance goals in the most economical way. Allan has a passion for working on complicated computing problems and isn’t afraid of trying varied technologies to … Read More → "Allan Cantle"

It’s Not All About the FPGA Anymore

Introduction

FPGA logic design no longer rules the project schedule like it once did. Twenty years ago, implementing the logic in 20 and 24-pin programmable logic devices, such as 22V10s or PAL16R8s, was tricky, given the state of programmable logic tools at the time, but doing so certainly didn’t consume the lion’s share of the overall design effort. Back then, the deciding factor in project schedules was typically the design of the PCB onto which those devices were placed. As the sophistication of programmable devices has increased – evolving … Read More → "It’s Not All About the FPGA Anymore"

Mapping MAPLD

It’s difficult for a technical conference to get just the right balance. Too much tradeshow, not enough industry participation; too many irrelevant sessions, too many times over the same topic; not enough attendees, too many attendees… it’s like trying to hit your design constraints for power, cost, area, performance, and reliability all at the same time, while still meeting your schedule. You struggle to reach one goal only to find out that you’ve slipped behind on the others. It’s a fight to find a creative solution that will converge.

< … Read More → "Mapping MAPLD"

Migrating FPGA Virtual Gates to MROM Reduces Reliability Risk

Interest in FPGA reliability is not restricted to SEU environments. The US critical infrastructure, for example, often demands 24/7 operations and thus hi-reliability is frequently sought and very few, if any, of the infrastructure components are in SEU environments.

System failures are largely attributed to software-level errors such as unexpected input values, timing violations, and I/O shortfalls. To decrease the probability of system failure, many specialized, checking functions can be performed during runtime to make the software error-resilient. However, system performance suffers because the checking functions consume processor cycles that would otherwise be used for the mission … Read More → "Migrating FPGA Virtual Gates to MROM Reduces Reliability Risk"

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