feature article
Subscribe Now

More ARMs Than a Hindu Goddess

After shipping 15 billion chips you’d think the cocky computer cowboys from Cambridge would be finished, right? Not on your life, pardner. They’ve got more tricks up their collective sleeve than a saloon gambler with a seat against the wall. They just keep dealin’ and we keep ante’ing up.

The newest ace in the hole is the Cortex-A5, announced today. The –A5 fills the enormous (not really) gap between the Cortex-A8 and ARM’s older designs in the ARM9 and ARM11 family. (For some background on ARM’s processor nomenclature, see Embedded Technology Journal, August 25, 2009.)

The A5, codenamed Sparrow, is mostly just a watered-down A8. It’s slower, and therefore cheaper, than its sibling, but still faster than anything in the Cortex R-series or the older numerically designated processors. As such, the A5 is now the entry point into the top-range A-series of ARM processors.

Is That An African or European Sparrow?

ARM has so many processor offerings now that, like BMW, it’s in danger of running out of model numbers. The A5 is faster than either the ARM9 or ARM11 cores, while beating both on power consumption. Silicon area is about the same as an ARM926EJ-S, although, really, most microprocessor cores today are so small that their size is irrelevant. Caches and peripherals take up more silicon area than the processor on all but the most over-provisioned chips. Even so, ARM likes to make a big deal about its compactness, one of the few times you’ll see grown men arguing over who has the smallest unit.

Performance improves, of course, with the A5 over its predecessors. What would be the point, otherwise? ARM’s corporate propaganda points out that an A5 fabricated in 40-nm silicon is three times faster than an ARM9 in 130-nm geometry while consuming half the power and occupying one-fifth the silicon area. While that’s undoubtedly all true, it’s also fairly meaningless. Every processor gets smaller, faster, and more power-efficient with changes in silicon geometry; our industry depends on it. ARM also crows about the A5’s space and power efficiency versus Intel’s Atom core, which is a total gimme. Being more efficient than an x86 processor is like being skinnier than a weightlifter: true, but no great achievement.

I’m not suggesting the Cortex-A5 isn’t a good processor. It may even be a great processor. But ARM undersells its benefits somewhat by comparing it to Intel and to its own elderly products. We would expect newer processors to be better in some dimension; anything less would be unworthy of the ARM brand. 

And the A5 is a very good processor, especially if you’re making relatively high-end consumer electronics. It’s got all the software and tool support that have made ARM the de facto architecture choice for many engineers. It’s fast, at about 1 GHz clock frequency in reasonable process geometries. It’s even multiprocessor (not multicore) capable if you’re into that. And it comes with Neon and TrustZone for accelerating media processing and security, respectively.

So what separates the A5 from the A8? That’s a good question, and ARM is a little coy on the details. One gets the impression that the A5 is really just a watered-down A8, with a shorter pipeline and some features removed. That’s fine. In fact, it’s a good business strategy. If Lexus is just a Toyota with leather seats, the A8 is really just the A5 with some more bells and whistles. In both cases, the lower-end model allows customers to buy into the brand without breaking the bank.

In ARM’s case, it wants existing licensees of the ARM9 and ARM11 to re-up with the Cortex-A5. That keeps the license revenue flowing (no small matter) and moves the customer base to the newer code base and architecture. The more licensees that use the newer processor cores, the easier they’ll be to support. Of course, there’s the minor issue of the A5 license fee, and ARM is understandably reticent about discussing the details of that. Plan on writing a six-figure check, plus royalties for many years to come. That’s the price of staying current in this high-stakes game.

Leave a Reply

featured blogs
Feb 27, 2021
New Edge Rate High Speed Connector Set Is Micro, Rugged Years ago, while hiking the Colorado River Trail in Rocky Mountain National Park with my two sons, the older one found a really nice Swiss Army Knife. By “really nice” I mean it was one of those big knives wi...
Feb 26, 2021
OMG! Three 32-bit processor cores each running at 300 MHz, each with its own floating-point unit (FPU), and each with more memory than you than throw a stick at!...
Feb 26, 2021
In the SPECTRE 20.1 base release, we released Spectre® XDP-HB as part of the new Spectre X-RF simulation technology. Spectre XDP-HB uses a highly distributed multi-machine multi-core simulation... [[ Click on the title to access the full blog on the Cadence Community si...

featured video

Designing your own Processor with ASIP Designer

Sponsored by Synopsys

Designing your own processor is time-consuming and resource intensive, and it used to be limited to a few experts. But Synopsys’ ASIP Designer tool allows you to design your own specialized processor within your deadline and budget. Watch this video to learn more.

Click here for more information

featured paper

Functional Safety-Relevant Wireless Communication in Automotive Battery Management Systems

Sponsored by Texas Instruments

With increasing energy density in HEV/EVs, effective battery management and monitoring is essential to avoid any kind of hazards related to overvoltage or overtemperature. This paper explores achieving ASIL D functional safety compliance while using a wireless battery management system.

Click here to download the whitepaper

Featured Chalk Talk

Mom, I Have a Digital Twin? Now You Tell Me?

Sponsored by Cadence Design Systems

Today, one engineer’s “system” is another engineer’s “component.” The complexity of system-level design has skyrocketed with the new wave of intelligent systems. In this world, optimizing electronic system designs requires digital twins, shifting left, virtual platforms, and emulation to sort everything out. In this episode of Chalk Talk, Amelia Dalton chats with Frank Schirrmeister of Cadence Design Systems about system-level optimization.

Click here for more information