Today’s complex, high-pin-count FPGAs present a special problem for board designers as issues of timing, routability, cost, and signal integrity can defeat old-school “over … Read More → "FPGA – PCB Co-Design Done The Right Way (CHALK TALK)"
Today’s complex, high-pin-count FPGAs present a special problem for board designers as issues of timing, routability, cost, and signal integrity can defeat old-school “over the wall” design flows.
In this Chalk Talk, Amelia Dalton chats with Hemant Shah of Cadence about about bridging the gap between FPGA design and PCB design.
Read More → "FPGA – PCB Co-Design Done The Right Way"
Are your FPGAs outgrowing your tool flow? Join Amelia Dalton as she talks with Jeff Garrison of Synopsys about setting up your design tools for today’s more demanding FPGAs.
We’ll discuss how the size and complexity of today’s FPGAs demand … Read More → "Solving Today’s Tough FPGA Design Problems"
Today’s complex, high-pin-count FPGAs present a special problem for board designers as issues of timing, routability, cost, and signal integrity can defeat old-school “over the wall” design flows.
< … Read More → "CHALK TALK – FPGA – PCB Co-Design Done The Right Way."
Thinking of using multiple processors on FPGA-based systems? Join Amelia Dalton as she demystifies dual-processor development with Rey Archide of Xilinx.
The webcast explains how to manage the challenges associated with placing one or more processors in an embedded-system-on-FPGA. FPGAs are becoming very popular platforms for embedded systems designers, and Xilinx has a rich portfolio of tools and IP … Read More → "Dual-Processor FPGA Designs Made Easier"
Making sure the hardware version of your DSP algorithm is doing what you want can be a difficult task – particularly if you are doing high-performance algorithms that require hardware accelaneration … Read More → "CHALK TALK – Simplified Verification of DSP Algorithms in Hardware"
Read More → "CHALK TALK – Power Estimation in High-Level DSP Design Flow"
Making sure the hardware version of your DSP algorithm is doing what you want can be a difficult task – particularly if you are doing high-performance algorithms that require hardware accelaneration … Read More → "CHALK TALK Simplified Verification of DSP Algorithms in Hardware"
Today’s complex, high-pin-count FPGAs present a special problem for board designers as issues of timing, routability, cost, and signal integrity … Read More → "CHALK TALK – FPGA – PCB Co-Design Done The Right Way."
