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ESC Survival Kit

In deciding where to shoot your silver bullet, there are a variety of factors to consider. (Make sure your boss doesn’t read this part.) Is the conference in an exciting location? Does it have good parties? Are there excellent restaurants nearby? Does the subject matter of the conference match convincingly enough with your project that your manager can be persuaded to spring for the budget?

There are also smaller, more esoteric issues. (You can let the boss start reading again.) For example, if you’re working on high-reliability software in embedded systems for military … Read More → "ESC Survival Kit"

Go, Stop, Yield

Craig (not his real name) is the lead engineer on his company’s most important project. So far, Craig has been worth his weight in gold (which is about $1.6M assuming $550 per troy ounce at his current weight of 2916 troy ounces). Besides working out regularly to keep those unwanted troy ounces off, Craig keeps up with the very latest FPGA technologies so he can make solid decisions in creating his company’s new flagship electronic product.

This time, Craig chose a state-of-the-art 90nm FPGA as the centerpiece of his masterpiece. The product fit was perfect. Before this … Read More → "Go, Stop, Yield"

A Bunch of Babies

Sure, we’ve had a few years of comfort where C-based programming could solve the majority of embedded design problems, and we’ve even developed a respectable infrastructure of tools and IP to support that methodology. We also now have a legacy of previously developed C software libraries atop which we can coast along, just stitching together a few convenient APIs when we want to whip up a quick GUI or database. Our laziness and complacency remain secreted safely away while we manage to look like heroes to management by hammering out new applications with record speed. Times are … Read More → "A Bunch of Babies"

Are You Designing with Too Many Significant Figures?

Achieving timing closure in today’s increasingly large and complex digital integrated circuit designs – irrespective of whether they are realized using FPGA, Structured ASIC, or even Standard Cell ASIC fabric – is becoming evermore problematic with the latest design targets running at aggressive clock speeds.

The majority of today’s designers typically code in RTL using Verilog or VHDL. Also, there is some use of C/C++/SystemC coupled with behavioral synthesis technology in certain application areas. Unfortunately, both of these approaches have specific, but different, disadvantages associated with them. As we shall see, … Read More → "Are You Designing with Too Many Significant Figures?"

Ask for Whom the Bell Tolls

I was at DATE 2006, a tradeshow in Germany. My cell phone started buzzing with calls, voicemails and e-mail. People were stopping me on the show floor – pulling me aside, whispering rapidfire questions – always small variations on a theme. “Did you hear that LSI Logic is killing RapidChip? Do you think that structured ASIC is dead? Are other structured ASIC vendors pulling out as well? Will FPGAs wipe out the structured and platform ASIC space entirely? What’s Altera doing? What about ChipX? Isn’t AMI doing structured as well? Has eASIC been acquired yet? What have … Read More → "Ask for Whom the Bell Tolls"

Biting Bugs Back

In 1949, there was only one processor, and it was in a computer laboratory. Today, processors are ubiquitous; they are found in cars, phones, planes, satellites, routers, phone-switches, toys, cameras, refrigerators, and almost everything else. Inside those processors is an exploding quantity of software that is breaking the existing debugging methodologies. Late last year, Toyota recalled its Prius hybrid cars due to a software bug. Satellites are lost due to software bugs. Even heart pacemakers cause problems and fail due to software bugs. In 2002, the US National Institute of Science and Technology estimated that software quality problems were costing the … Read More → "Biting Bugs Back"

What Do You Tell Them?

I rolled into my own defeat with the resignation of a mortally wounded rabbit. “Gate arrays,” I replied, already knowing the next step of the dance. Then I made a futile attempt to divert him. “They’re chips used to…”

“Oh yes, that’s right, Gatorade.” he interrupted, determined to repeat the entire game despite my desire to resign. “I used to give that to my marching band members so they wouldn’t get dehydrated on hot days. Don’t remember it coming in chip … Read More → "What Do You Tell Them?"

Field Programmable Gate Arrays for Flexible and Fast Data Processing


Use of a generic FPGA board together with a powerful programming environment is investigated. It is demonstrated that high-performance real-time analysis is achieved at a reasonable cost. The system is simple to integrate with off-the-shelf acquisition systems such as LabVIEW. A flexible wavelet algorithm is programmed and is found to be considerably faster than the processor of the host computer. The flexibility of the processing unit makes it a promising tool for applications where ordinary desktop computers do not provide enough processing power.

Research-oriented experimental equipment must often offer high-performance … Read More → "Field Programmable Gate Arrays for Flexible and Fast Data Processing"

What Do You Tell Them?

My twenty-three-year-old eyes couldn’t muster the maturity to disguise my frustration. He sensed their weakness. It was what he was watching for. Even as I struggled in vain to regain my composure, he moved in for the kill. “What did you say again that your company does?” My father posed the question, fully aware of the answer, waiting with the patience of the hunter who has already cornered his prey for my inevitable self-destruction.

I rolled into my own defeat with the resignation of a mortally wounded rabbit. “Gate arrays,” I … Read More → "What Do You Tell Them?"

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