In addition to the anticipated performance improvements commensurate with the production release of a Xilinx tool suite, the release of ISE v12 software unveils significant innovations with far-reaching potential. A new power-optimization capability called intelligent clock gating can reduce dynamic power by up to 30%. An innovation called design preservation vastly improves the user’s ability to achieve and maintain timing closure and design repeatability. An intuitive, fourth-generation partial reconfiguration design flow has already begun proving its ability to enable designers to reduce the size, cost, and power of their designs. With the introduction of AXI4, Xilinx has enabled the creation of a vast, ecosystem-supported plug-and-play IP library for Xilinx FPGAs that provides easy access to new and existing IP of both the memory-mapped and data-streaming varieties.

These innovations deliver unparalleled value in the three most important criteria for next-generation FPGA designs: better power efficiency, increased productivity, and higher performance.

Power Optimization

Building on a well-known but often under-utilized power-optimizing design methodology called clock gating, ISE Design Suite v12 introduces the first automated, intelligent clock gating technology for FPGA design. With this capability, the tool automatically neutralizes unnecessary logic activity, reducing dynamic power usage up to 30%. ISE v12 software also introduces the fourth-generation partial reconfiguration technology, which, when combined with the design flow in ISE v12 software, provides a simple, intuitive approach to on-the-fly reuse of FPGA resources, creating additional opportunities to reduce power.

Productivity

ISE v12 software breaks new ground in design productivity enhancements with the introduction of design preservation—the ability to partition and lock down the placement and routing of timing-critical portions of a design, thus enabling the designer to achieve and maintain timing repeatability. This new partitioning technology figures prominently in the deployment of partial reconfiguration. ISE v12 software also introduces next-generation Advanced Microcontroller Bus Architecture (AMBA® protocol) IP, interconnect, and tool support. Xilinx has been intimately involved with ARM on the development of the updated version 4 open standard interface specification to enable the development and delivery of plug-and-play IP from Xilinx and third-party ecosystem providers—an advance that can provide the most valuable benefit to design productivity.

Performance

ISE v12 software supports production Spartan-6 and Virtex-6 FPGA devices and IP with fully optimized place-and-route and synthesis algorithms, improving Quality of Results (QoR) and greatly decreasing synthesis and implementation runtimes. An enhancement to SmartXplorer in the ISE v12 software release accelerates timing closure by enabling exploration of design strategies in the synthesis space.