The intelligent clock-gating optimization feature introduced in ISE Design Suite v12 greatly simplifies the effort to reduce dynamic power in FPGA designs. The traditional approach to clock-gating optimization used in ASIC design presupposes an intimate knowledge of the design, thereby virtually precluding optimization of legacy and third-party IP blocks. New tools, new steps, and complex timing analyses are typically required to compensate for the inevitable new “gated clocks” and the changes in logic that are produced.
In contrast, Xilinx intelligent clock-gating optimizations are automatically performed on the entire design, introduce no new tools or steps to the flow (compared to the default flow), and generate no changes to the existing logic or clocks that would alter the behavior or timing of the original design version.
Clock gating is a well-understood power optimization technique employed in both ASIC and FPGA designs to eliminate unnecessary switching activity. This method usually requires that the designers add a small amount of logic to their RTL code to disable or deselect unnecessarily active sequential elements-registers, for example. Despite the obvious value of reduced dynamic power afforded by this method, the designer faces significant challenges when attempting to perform these optimizations manually:
• Truly reducing activity in the design requires intimate knowledge of the design itself and typically requires numerous changes to the RTL.
• Most ASIC and FPGA designs today comprise some combination of new, legacy, and third-party IP circuit designs, but typically only the new designs are candidates for clock-gating optimizations. Designers rarely if ever attempt these optimizations on legacy and IP design. They usually do not have sufficient depth of knowledge about the design and operation of the legacy RTL code, and it requires too much time to manually develop meaningful clock-gating optimizations.
• Applying clock-gating optimizations usually requires the addition of more tools and more steps to the design flow and can precipitate the creation of an intricate set of new clocks requiring complex timing analyses (as is often the case for ASIC optimization). Unless the gains in power efficiency are sufficient and essential to the success of the design, the additional complexity and time can be prohibitive and add risk.
With the release of ISE® Design Suite v12, Xilinx has introduced an automated capability linked to the place-and-route portion of the standard FPGA design flow that uses a set of innovative algorithms to perform an analysis on all portions of the design (including legacy and third-party IP blocks). Having analyzed the logic equations to detect sourcing registers that do not contribute to the result for each clock cycle, the software utilizes the abundant supply of clock enables (CEs) available in the logic of Virtex-6 and Spartan®-6 FPGAs to create fine-grain clock-gating or logic-gating signals that neutralize superfluous switching activity.
