feature article
Subscribe Now

Enabling Low-Power EO/IR System Development with FPGAs and Image- and Sensor-Processing IP

Before embarking on the development of a next-generation electro-optical and infrared (EO/IR) system, it is important to not only understand the power and performance characteristics of the FPGA, but also the various functions developed both as IP and reference designs. Altera’s VIP Suite of MegaCore®functions provide sensor control and various image-processing capabilities, including buffering, scaling, filtering, and combining video streams in real time. Imagize’s FP-5500 compact video-processing engine offers sensor processing and image fusion on an Altera® Cyclone® FPGA platform, meeting system performance and size, weight, and power (SWaP) requirements for next-generation EO/IR systems. Implementing these functions on Altera’s Cyclone IV FPGAs can kick-start development efforts for nextgeneration EO/IR and display systems, as well as provide a canned solution for the “boring” aspects of system design, leaving the designer free to innovate on value-add functions.

Introduction

Military imaging systems are becoming increasingly sophisticated, incorporating multiple advanced sensors ranging from thermal infrared, to visible, to even ultraviolet focal planes. Not only do these sensor outputs need to be corrected, interpolated, etc., often images from multiple sensors must be combined and further processed for local display and/or for transmission. Figure 1 shows a high-level block diagram of a typical signal chain implemented in an electro-optical infrared (EO/IR) system. As shown, the processed image is compressed many times (usually lossless) before being transmitted over a communications link.
 

Whitepaper_enabling-1.jpg
Figure 1. Typical Signal Chain for an EO/IR System
 

Combining exceptional image quality with low power consumption is the key challenge when designing EO/IR systems. For hand-held and wearable systems, such as night-vision goggles (NVGs) or weapon sights, the critical specification is often the number of hours a unit can run on AA batteries. According to military estimates, “An infantry soldier requires one AA battery an hour in combat.” (1)

Low-power FPGAs are the platform of choice for almost all state-of-the-art EO/IR systems because they meet the needs for programmability, real-time video-processing performance, and low power consumption. In fact, each successful generation of low-power  FPGAs have featured both lower static and dynamic power consumption by utilizing a combination of architectural enhancements and lower core voltages. As the process technology continues to march downwards, the average power consumed by these FPGAs has dropped 30% or more each generation, as shown in Figure 2.
 

Whitepaper_enabling-2.jpg
Figure 2. Power Reduction in Successive Generations of Low-Power FPGAs of Comparable Density
 

Offering up to 150,000 logic elements (LEs), Cyclone IV FPGAs consume up to 30% less total power than the previous generation. This low-power, programmable silicon platform provides ample computational power to implement the sensor-control and image-processing algorithms required for most HD video processing systems.

Author:  Suhel Dhanani, Sr. Manager, DSP Marketing

Juju Joyce, Sr. Strategic Marketing Engineer, Military and Aerospace Group

Mr. Dhanani is responsible for DSP product marketing. He has over 15 years of industry experience in semiconductors, and has completed a graduate certificate in Management Science from Stanford University and holds MSEE and MBA degrees from Arizona State University.

Leave a Reply

featured blogs
Apr 26, 2024
LEGO ® is the world's most famous toy brand. The experience of playing with these toys has endured over the years because of the innumerable possibilities they allow us: from simple textbook models to wherever our imagination might take us. We have always been driven by ...
Apr 26, 2024
Biological-inspired developments result in LEDs that are 55% brighter, but 55% brighter than what?...
Apr 25, 2024
See how the UCIe protocol creates multi-die chips by connecting chiplets from different vendors and nodes, and learn about the role of IP and specifications.The post Want to Mix and Match Dies in a Single Package? UCIe Can Get You There appeared first on Chip Design....

featured video

MaxLinear Integrates Analog & Digital Design in One Chip with Cadence 3D Solvers

Sponsored by Cadence Design Systems

MaxLinear has the unique capability of integrating analog and digital design on the same chip. Because of this, the team developed some interesting technology in the communication space. In the optical infrastructure domain, they created the first fully integrated 5nm CMOS PAM4 DSP. All their products solve critical communication and high-frequency analysis challenges.

Learn more about how MaxLinear is using Cadence’s Clarity 3D Solver and EMX Planar 3D Solver in their design process.

featured paper

Designing Robust 5G Power Amplifiers for the Real World

Sponsored by Keysight

Simulating 5G power amplifier (PA) designs at the component and system levels with authentic modulation and high-fidelity behavioral models increases predictability, lowers risk, and shrinks schedules. Simulation software enables multi-technology layout and multi-domain analysis, evaluating the impacts of 5G PA design choices while delivering accurate results in a single virtual workspace. This application note delves into how authentic modulation enhances predictability and performance in 5G millimeter-wave systems.

Download now to revolutionize your design process.

featured chalk talk

PIC® and AVR® Microcontrollers Enable Low-Power Applications
Sponsored by Mouser Electronics and Microchip
In this episode of Chalk Talk, Amelia Dalton and Marc McComb from Microchip explore how Microchip’s PIC® and AVR® MCUs are a game changer when it comes to low power embedded designs. They investigate the benefits that the flexible signal routing, core independent peripherals, and Analog Peripheral Manager (APM) bring to modern embedded designs and how these microcontroller families can help you avoid a variety of pitfalls in your next design.
Jan 15, 2024
14,638 views