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STMicroelectronics and ARM Team Up To Power Next-Generation Home Entertainment

ST adopts ARM Cortex-A9 multicore processor to deliver high-performance SoCs for an enhanced HDTV experience for consumers, while raising the bar for power efficiency in home entertainment equipment

GENEVA and CAMBRIDGE, England, Oct. 28 /PRNewswire-FirstCall/ — STMicroelectronics (NYSE:STM) , one of the world’s leading set-top-box chip makers, and ARM [; (NASDAQ:ARMH) ], announced today that ST has adopted the ARM® Cortex(TM)-A9 MPCore(TM) processor, in addition to the Mali®-400 graphics processor, for its upcoming set-top-box and digital TV system-on-chip (SoC) ICs.
The Cortex-A9 MPCore processor provides ST with the scalable high performance … Read More → "STMicroelectronics and ARM Team Up To Power Next-Generation Home Entertainment"

Symmetricom Announces Key Enhancements to Q-Advisor Digital Video Monitoring and Management Software

Symmetricom’s Q-Advisor Delivers Advanced Reporting of Digital Video Quality for Cable Providers; Featured at SCTE Cable-Tec Expo – October 28-30, 2009 – Denver, Colo.

SAN JOSE, Calif. — Oct. 28, 2009 — Symmetricom®, Inc. (NASDAQ: SYMM), a worldwide leader of precise time, synchronization and video quality management technologies that optimize next generation networks, today announced key enhancements to Q-Advisor, its Network Operations Center (NOC) management software for its V-Factor® Quality of Experience (QoE) monitoring platform. New advanced reporting capabilities enable video monitoring operators to prioritize specific troubleshooting actions and manage high impact outages, saving time, … Read More → "Symmetricom Announces Key Enhancements to Q-Advisor Digital Video Monitoring and Management Software"

Intel and Numonyx Achieve Research Milestone With Stacked, Cross Point Phase Change Memory Technology

New Research Discovery Paves Way for Scalable, Higher Density Phase Change Memory Products

2009 International Electron Devices Meeting
SANTA CLARA, Calif. & GENEVA–(BUSINESS WIRE)–Intel Corporation and Numonyx B.V. today announced a key breakthrough in the research of phase change memory (PCM), a new non-volatile memory technology that combines many of the benefits of today’s various memory types. For the first time, researchers have demonstrated a 64Mb test chip that enables the ability to stack, or place, multiple layers of PCM arrays within a single die. These findings pave the way for … Read More → "Intel and Numonyx Achieve Research Milestone With Stacked, Cross Point Phase Change Memory Technology"

Synopsys announces 40th DesignWare audio codec IP

Broad DesignWare audio IP portfolio shipped in more than 100 million units

MOUNTAIN VIEW, Calif.—October 28, 2009— Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the availability of its 40th audio codec IP with the release of the DesignWare(r) 96 dB Hi-Fi Audio IP in the SMIC 65-nanometer (nm) process. Synopsys has been a leading provider of audio IP for more than twelve years and provides designers with high-quality audio IP solutions supporting 20 different process nodes, from 180-nanomenter (nm) to 65-nm processes and with performance … Read More → "Synopsys announces 40th DesignWare audio codec IP"

NVIDIA adopts Synopsys Yield Explorer to reduce time to volume

Design-centric yield management enables product engineers to achieve rapid yield ramp and provide cost-effective yield control in volume production

MOUNTAIN VIEW, Calif.—October 28, 2009— Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that NVIDIA Corp. has adopted Synopsys’ Yield Explorer solution for yield analysis and yield ramp. NVIDIA, which invented the graphics processing unit, selected Yield Explorer because of its ability to coherently combine and cross-correlate large volumes of data from the design, fab and test domains to quickly identify dominant failure mechanisms. This … Read More → "NVIDIA adopts Synopsys Yield Explorer to reduce time to volume"

Living With Ambiguity: The Other HLS

 

As the discussion wound down, the meeting leader asked them all about their capabilities as a source for RTL generation.

Both Matlab and SystemC jumped into action and started expounding at the same time. “You can use Simulink to add timing and system elements…” “…pre-mapped cells to RTL…” “… directly to FPGAs…” “… avoiding endless timing closure iterations…”

But at the same time, C chimed in with, “Oh, I’ve been doing … Read More → "Living With Ambiguity: The Other HLS"

Who is Responsible for Safety?

We have all heard the (apocryphal) story of the motor-home driver who sets the cruise control and then goes back to make coffee, since he/she was told that the cruise control looked after everything. The story has been around the internet for years and while wholly untrue (at least I hope it is) it still has, at its heart, one of the essential questions of safety – who is responsible? Presumably the cruise control did exactly what it was meant to do, control the speed of the vehicle, but this wasn’t what the driver expected … Read More → "Who is Responsible for Safety?"

Once More, With Feeling

Xilinx and Altera have each recently and respectively announced agreements with ARM and MIPS.  While these announcements may be coincidental, they trigger a decade-old feeling of digital-design deja vu.  A mere ten years ago, with great fanfare, Altera introduced the ill-fated Excalibur – the Titanic of FPGA families – and ushered in the era of programmable systems-on-chip with FPGAs.  Like the Apple Lisa and Newton, the product itself failed, but the concept it introduced went on to flourish.  Now, ten years later, that chilly feeling is back.

Before we drop too much into what we … Read More → "Once More, With Feeling"

FPGA IP: Keeping Your Device Options Open

The use of third-party intellectual property (IP) is all but a necessity for most FPGA designs today. The complexity of platform designs as symbolized in Figure 1, the sophistication of modern FPGA architectures, and time-to-market pressures combine to force engineers to call on proven IP elements for at least some the standard functionality within their emerging designs. They rely on IP ranging from storage elements and arithmetic cores to system-level IP offering broader functionality including processors, interfaces, peripherals, and more.

The design challenge is twofold: first, to use these types of IP effectively for the current project; and … Read More → "FPGA IP: Keeping Your Device Options Open"

Renesas Technology to Release SH7777 (SH-NaviJ3) SoC for Dashboard-mounted Car Navigation and Infotainment Systems Offering Enhanced Audio and Video Functions

— OpenGL® ES1.1, the industry-standard programming interface for graphics processing, is supported, allowing sophisticated and flexible 3-D graphics applications to be developed in less time–

SAN JOSE, Calif.–(BUSINESS WIRE)–Renesas Technology America, Inc., today announced the SH7777 (SH-NaviJ3), the third product in the SH-NaviJ Series of system-on-chip (SoC) devices for compact portable navigation and infotainment systems and low- and mid-priced dashboard-mounted car navigation and infotainment systems. It speeds up development through OpenGL® ES1.1*1 support and offers enhanced multimedia functions such as terrestrial digital TV broadcast support. The SH7777 (SH-NaviJ3) makes it possible for developers … Read More → "Renesas Technology to Release SH7777 (SH-NaviJ3) SoC for Dashboard-mounted Car Navigation and Infotainment Systems Offering Enhanced Audio and Video Functions"

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