Altera’s flash memory configuration controller provides an alternative configuration solution for high-density FPGA-based designs. With the flexibility to use a bigger flash memory to store more configuration data, designers can implement the flash memory controller in Altera’s MAX® II, MAX 3000A, or MAX 7000 devices for use in Stratix series, Arria series, and Cyclone series FPGAs.
Introduction
Configuration bitstream sizes are increasing with the introduction of higher-density FPGAs. This increase requires larger configuration devices to store the data and configure these FPGAs. As an alternative to using larger configuration devices, designers can use flash memory to store configuration data. To use flash memory to perform configuration, designers must use a flash memory configuration controller, which also allows the implementation of a remote system upgrade configuration scheme in the design. This paper shows how to implement the flash memory controller in Altera’s MAX II, MAX 3000A, or MAX 7000 devices.
Configuration Controller Features
Designers can use the MAX series configuration controller for the following functions: read configuration data from a flash memory, configure Altera® FPGAs, remote System Upgrade Configuration (only in Altera’s Stratix® series, Arria® series, and Cyclone® series FPGAs), and configuration from multiple pages of configuration data. FPGA_PGM pins allow designers to choose one of the configuration pages to configure FPGAs.
The MAX series configuration controller supports the following configuration modes: Fast Passive Parallel (FPP) Mode (with and without decompression), Passive Serial (PS) Mode (with and without decompression), Passive Parallel Asynchronous (PPA) Mode, and Remote System Upgrade (only in Stratix series, Arria series, and Cyclone series FPGAs). Figure 1 shows the flash memory controller block diagram.
Configuration Controller Operation
Figure 2 shows how the configuration controller executes the basic operation when it is powered up.
Page Selection for Configuration Controller
Flash memory can store multiple configuration pages in different addresses. The configuration controller allows the designer to select which configuration page in the flash memory to load during the configuration. To determine which page to load, the controller reads the FPGA_PGM pin in non-remote upgrade mode or reads the PGM pin in remote upgrade mode. A Stratix series, Arria series, or Cyclone series FPGA controls the PGM pins through the FPGA’s remote system upgrade block. Designers can control FPGA_PGM pins using DIP switches or other devices.
Read and Process Configuration Data
The configuration controller reads configuration data through the flash_DATA [7..0] data bus, and optionally through the flash_DATA [15..8] data bus. In PS mode, the configuration controller sends the serial configuration bitstream through the fpga_DATA0 pin. In FPP, FPP with decompression, and PPA mode, the configuration controller sends the configuration data through the fpga_DATA[7..0] data bus. During the configuration process, the configuration controller executes the following processes: PS Mode: Reads one byte (eight bits) or two bytes (16 bits) of configuration data from flash memory and serializes the data, Generates the DLCK signal and sends one bit of configuration data for every DLCK signal, Reads the next byte(s) of configuration data from flash memory after 8 or 16 DLCK signals. FPP Mode: Reads one byte (eight bits) or two bytes (16 bits) of configuration data from flash memory.
Author: Rafael Camarota, Non-Volatile Product Line Manager, Low-Cost Products
Mr. Camarota joined Altera in 2002, where he is responsible for all CPLDs, and configuration products. He has more than 25 years of semiconductor experience and in the PLD industry. He holds a BSEE from Carnegie-Mellon University, and has over 25 patents relating to programmable logic circuits.
