As mask prices and NRE costs rise to exorbitant levels, the ASIC route becomes increasingly unrealistic for many applications, especially in low- to medium-volume production quantities. Design starts using ASICs have plummeted from a high of over 11,000 in 1997 to below 4,000 in 2003 (Source: Gartner Dataquest). With the advent of innovative FPGA architectures incorporating embedded processors, memory blocks and DSP functions, many designers who depended on ASIC methodologies are turning to FPGAs for new generations of complex designs. The problem is that, increasingly, these designers are the same person, i.e., one day they are designing an ASIC and the next … Read More → "Does Single-pass Physical Synthesis Work for FPGAs?"
A few weeks ago, in our “What’s your Persona?” feature article, we discussed the fact that Xilinx is creating new divisions for DSP and embedded processing. We speculated that the idea of focusing on specific categories of new potential FPGA customers, creating groups inside the FPGA company that understand the design challenges and speak the technical jargon of each emerging subculture, would be a compelling strategy.
We then decided to test that theory by asking you to drop … Read More → "Engineers Speak Out"
Traditionally, FPGAs are not considered suitable for low-power application design because of higher quiescent power, significant energy dissipation during start-up, and higher dynamic power due to longer interconnects and overheads for reconfigurability. However, with advances in FPGA manufacturing technologies and growing demand for feature-rich mobile applications in both civilian and military communities FPGAs are being considered an attractive device for applications deployed in power-constrained environments. Some of the reasons for considering FPGA for energy efficient application design are:
— In general, FPGAs are denser, use lower supply voltage, and provide more computation per Watt than … Read More → "Energy Efficient Application Design using FPGAs"
Wally Rhines doesn’t follow the crowd. He’s made a career of betting on the dark horse and tackling the unpopular assignment. As the semiconductor industry’s version of Warren Buffet, Rhines has consistently picked the out-of-favor or under-performing business with big turnaround potential. When Wally took his position as CEO of Mentor Graphics in 1993, he was assuming the helm of a ship that many believed was sinking fast. Mentor had launched its epic “Falcon Framework” with great fanfare, only to be besieged by unhappy customers in a market that was moving fast away from frameworks and toward … Read More → "Wally Rhines"
Two hulking masses of mechanized metal sit separated by 40 feet in a bulletproof Lexan cage lined by twelve-inch iron girders. The green light flashes and the starting buzzer sounds. Industrial electric motors on both fighting robots spin outer armored shells to rotational speeds near 1,000 RPM. The two ‘bots rush toward each other, colliding in a spectacular spray of molten metal. Broken bolts ricochet off the protective barrier.
The crowd at the 2004 Robot Fighting League ( … Read More → "Metal Mangling Mayhem"
Over the course of the first year, we’ve had a tremendous amount of feedback and input from you, our readers. We’ve also done several formal surveys and studies that have spanned the entire year, with follow-up e-mails to many of you to clarify just what you meant by assertions like “…works very reliably except when it fails.” Here, then, we are proud to present back to you some of the things you told us – your favorite suppliers and products in a variety of categories – in the form of awards.</ … Read More → "First Annual FPGA Journal Awards"
Light the candles …er… candle, sing the song, pummel the piñata, and uncork the champagne. It’s been one year since FPGA Journal’s first edition, and it’s time to look back and celebrate our inaugural year. Our lights first came on October 1, 2003 when FPGA Journal Update Volume I Number 1 went out to about 1,000 early subscribers. During the year that followed, our newsletter subscription base has grown to over 8,500 and our web audience to over 34,000 readers in 87 countries.
We’ve worked hard over the past year … Read More → "Happy Birthday To Us!"
I once commented to a colleague that every EDA presentation ever given follows a basic script:
Presenter: Moore’s Law!
Audience: Oh no! What shall we do?
Presenter: Don’t worry. We have a new EDA tool that’ll save you.
Audience: What a relief.
If that is true, then every semiconductor presentation might have an analogous script:
Presenter: Moore’s Law!
Audience: Oh boy! What do we get?
Presenter: Bigger, faster, cheaper.
This week, we’ … Read More → "Cheap Gate Update"
With the ever-increasing size and density of ASIC, conventional simulation-based verification has become a bottleneck in the project development cycle. In conventional verification, the simulation time steadily increases as the design matures in terms of bug count.
The verification community has resorted to different methodologies to overcome this. They are trying to reduce the development time by introducing Verification Components and Hardware Verification Languages (HVL). These help in terms of reusability but do not attend to the issue of simulation time. On one side, where the HVL provides better features such as higher … Read More → "Accelerating ASIC Verification with FPGA Verification Components"
It never makes the marketing materials. You don’t see an ad saying “New Super RISC Core is Stickier than Ever!” There is generally no mention of the word “sticky” in datasheets, white papers, or application notes. Suppliers of Intellectual Property (IP) cores (the overly-broad label that’s commonly applied to pre-engineered components that you can drop into your design, saving time, errors, and design effort) tout the speed, configurability, reliability, density, and power efficiency of their offerings, but never the “stickiness.” Unless you listen carefully to conversations in hallways, meeting … Read More → "Sticky Business"