EVE Adds Support for TLM-2.0 to ZeBu Hardware-Assisted Verification Platforms
June 1, 2010
SAN JOSE, CALIF. –– June 1, 2010 –– EVE, the leader in … Read More → "EVE Adds Support for TLM-2.0 to ZeBu Hardware-Assisted Verification Platforms"
Lattice Expands Hot-Swap Application Coverage For Power Manager Devices
June 1, 2010
HILLSBORO, OR — JUNE 1, 2010 — Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the addition of a new, higher performance device to its second generation Power Manager II product family. The ispPAC®-POWR1220-02 device integrates a higher voltage charge pump with programmable current to control MOSFETs in Hot-swap and Sequencing applications. The new device is pin compatible with existing Power Manager II devices and integrates power management functions that typically require multiple ICs, including Hot-swap Controllers, Reset Generators, Voltage Supervisors, Sequencers and Trackers. The ispPAC-POWR1220-02 also integrates Analog-to-Digital Converter (ADC) ICs used for power supply voltage … Read More → "Lattice Expands Hot-Swap Application Coverage For Power Manager Devices"
How Many Times Does CPU Go Into FPGA?
June 1, 2010
It’s déjà vu all over again. An FPGA company is embedding a 32-bit microprocessor into its FPGAs and calling it a “programmable system on a chip.”
Whoa, dude. Nasty flashback, huh?
Didn’t we just see Actel do this with its SmartFusion chips? And didn’t Altera try this back in the day with Excalibur? And doesn’t Cypress make pSoC devices that look just like that? And – hey, wait a minute! – didn’ … Read More → "How Many Times Does CPU Go Into FPGA?"
From Simulation to Emulation
June 1, 2010
Last year I tried to wade through the world of emulation to untangle it a bit. It all seemed so simple at the time. Once I had it untangled, that is. Problem is, I only thought I had untangled it. Cadence recently announced a “unification” (there’s that word again) between simulation, simulation … Read More → "From Simulation to Emulation"
Escaping from the Silo
June 1, 2010
Background – An Imperfect World
In an ideal world, EDA tools would represent a perfect match for the chip engineer’s needs, and their use model would be architected to match his design flow rather than the other way around. In the real, Perl-script infested world, EDA tools are islands between which users must build their own bridges. Moves toward data consistency help to some extent, but beyond that things become very cumbersome. Decisions made to address one problem, let’s say power consumption, can have an adverse affect on … Read More → "Escaping from the Silo"
Docea announces power and thermal modeling and analysis capabilities for Aceplorer, previews AcePowerModeler to close loop between implementation and architectural modeling at 47th DAC
May 28, 2010
Moirans-Grenoble, France – May 26, 2010 – Docea Power, the design-for-low-power company that delivers software solutions for power and thermal analysis at the architectural level, today announced a new version of its system-level power and thermal modeling … Read More → "Docea announces power and thermal modeling and analysis capabilities for Aceplorer, previews AcePowerModeler to close loop between implementation and architectural modeling at 47th DAC"
MIPS Technologies and its Ecosystem Highlight Solutions for Next-Generation SoCs at COMPUTEX TAIPEI
May 27, 2010
COMPUTEX TAIPEI, Taiwan – May 27, 2010 – MIPS Technologies, Inc. (NASDAQ: MIPS), a leading provider of industry-standard processor architectures and cores for digital consumer, home networking, wireless, communications and business applications, announced its program of events during COMPUTEX TAIPEI, being held June 1-5 at the Taipei World Trade Center (TWTC) and Taipei International ConventionCenter (TICC). During the show, MIPS Technologies will deliver multiple presentations in a range … Read More → "MIPS Technologies and its Ecosystem Highlight Solutions for Next-Generation SoCs at COMPUTEX TAIPEI"
TSMC Announces 0.18-Micron Automotive Grade Embedded Flash IP
May 27, 2010
HSINCHU, Taiwan, R.O.C., May 26 /PRNewswire-FirstCall/ –Taiwan Semiconductor Manufacturing Company, Ltd. (TWSE: 2330, NYSE: TSM) today announced the 0.18-micron automotive Embedded Flash IP as its second generation Embedded Flash IP that passed AEC-Q100 product qualification requirements for a wide range of automotive applications.
TSMC’s 0.18-micron automotive Embedded Flash IP macro features 27 percent area reduction compared to an equivalent 0.25-micron Embedded Flash IP. The 0.18um technology generation hits a cost and performance sweet spot as vast amount of IPs have been developed for many applications. The addition of this 0.18-micron automotive qualified Embedded Flash IP enables … Read More → "TSMC Announces 0.18-Micron Automotive Grade Embedded Flash IP"
TSMC Announces 0.18-Micron Automotive Grade Embedded Flash IP
May 27, 2010
HSINCHU, Taiwan, R.O.C., May 26 /PRNewswire-FirstCall/ –Taiwan Semiconductor Manufacturing Company, Ltd. (TWSE: 2330, NYSE: TSM) today announced the 0.18-micron automotive Embedded Flash IP as its second generation Embedded Flash IP that passed AEC-Q100 product qualification requirements for a wide range of automotive applications.
TSMC’s 0.18-micron automotive Embedded Flash IP macro features 27 percent area reduction compared to an equivalent 0.25-micron Embedded Flash IP. The 0.18um technology generation hits a cost and performance sweet spot as vast amount of IPs have been developed for many applications. The addition of this 0.18-micron automotive qualified Embedded Flash IP enables … Read More → "TSMC Announces 0.18-Micron Automotive Grade Embedded Flash IP"
Mentor Graphics Calibre Co-Development of TSMC’s iLVS Simplifies Modeling of Advanced Devices for Physical Verification
May 27, 2010
WILSONVILLE, Ore., May 27, 2010—Mentor Graphics Corporation (NASDAQ: MENT) today announced that the Calibre® nmLVS product now provides comprehensive support for the iLVS interoperable rule specification used by TSMC for new design kits. This allows customers to define and customize complex IC design rules, as needed, while maintaining compliance with TSMC specifications and allowing seamless adoption of EDA vendor performance optimizations.
The iLVS specification, which was co-developed by Mentor and TSMC, separates the rule definition syntax from underlying rule implementations. This allows Mentor to optimize the underlying implementation, reducing the need for users to tune the … Read More → "Mentor Graphics Calibre Co-Development of TSMC’s iLVS Simplifies Modeling of Advanced Devices for Physical Verification"
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