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How Many Times Does CPU Go Into FPGA?

It’s déjà vu all over again. An FPGA company is embedding a 32-bit microprocessor into its FPGAs and calling it a “programmable system on a chip.”

Whoa, dude. Nasty flashback, huh?

Didn’t we just see Actel do this with its SmartFusion chips? And didn’t Altera try this back in the day with Excalibur? And doesn’t Cypress make pSoC devices that look just like that? And – hey, wait a minute! – didn’t Xilinx already try this once before?

Guilty on all counts. The CPU-with-FPGA mashup is apparently such a compelling concept that no one can oppose it. Resistance is futile. One chip vendor after another is held in thrall, mesmerized by the wondrous rewards just out of reach. But the Sirens’ song has caused more than one vendor to crash against the rocks of engineering reality. Embedded designers just don’t like FPGAs with CPUs inside. 

If at First You Don’t Succeed…

As Dick Selwood wrote in FPGA Journal (“A Platform to Bridge a Gap?” May 4, 2010), Xilinx is coming back to the table for seconds – of abuse, perhaps. Or maybe to right ancient wrongs. Either way, the company is peeling back the layers of disclosure on a new product family coming out late next year. The new chips (which don’t have an official brand name yet) will combine Xilinx’s familiar FPGA fabric with ARM’s equally familiar microprocessors. Yes, we’ve seen this combination before. We’ve even seen it from this company before. But this time it’s different. Really.

Here’s what we know: the new chips will combine two ARM Cortex-A9MP microprocessor cores onto a single chip, along with various amounts of programmable FPGA fabric. The FPGA logic and the CPU will be programmable separately. FPGA configuration will be handled by the processor(s) directly, not by a serial ROM or other automatic method. In other words, you have to tell the FPGA you want it configured. That’s very un-FPGA-like.

Xilinx didn’t skimp on the processors, either. The Cortex-A9 is ARM’s top of the line, and the A9MP is the extra-special multiprocessor version, and they both come with the Neon DSP accelerator. Clock speeds are expected to be in the 800-MHz range, so they won’t be slow. The chips will be built in an aggressive 28-nm process tweaked for low power instead of high speed, but even so, that’s a fast-moving pair of processors.

Some peripherals will be hard-wired into the chips, such as Ethernet, USB, UARTs, and so forth. You’ll be able to add more peripherals through the FPGA fabric, and all will be connected via ARM’s AXI bus interface. That means you should be able to buy (or develop) semi-standard peripherals with AXI interfaces.

Pricing? Don’t know yet. Size or logic capacity? Wait and see. Time frame? Samples aren’t expected until the back half of 2011, which is more than a year away. So why is Xilinx spilling the beans now? Possibly to piggyback on Actel’s recent SmartFusion rollout or… just maybe… to get a jump on a similar announcement from arch-rival Altera. 

Why Didn’t This Work the First Time?

So what’s different this time? Xilinx has embedded processors in its FPGAs before. So has Altera. And so have smaller FPGA firms like Actel, Atmel, and Cypress. What makes Xilinx think this new product line will fare any better than its predecessor?

We don’t know what Xilinx is thinking, but there are some good reasons why its previous generation failed to live up to expectations and why the new ones just might work.

For starters, the old chips had PowerPC processors inside and the new ones will have ARM. I’m not saying ARM is better than PowerPC, but it sure is a lot more popular. ARM-based processors are even more popular than Intel’s x86 chips. ARM’s legion of licensees ship something like five times as many microprocessors as Intel does. That’s a lot of silicon, and a lot of (presumably) happy programmers writing ARM code. Compare that to PowerPC, which has considerably more limited market appeal, and you begin to see the difference. Just based on dumb probability and statistics, Xilinx’s new ARM-based chips will likely find more customers than the PowerPC products did.

Then there’s the price. We’ll have to take Xilinx’s word on this one, but the company is making noises that the new ARM-based chips will be priced “reasonably.” That certainly wasn’t true of the old PowerPC-based chips. Those suckers were expensive. Not only were you buying a big Virtex-II FPGA (which was an expensive chip to begin with), you were also paying a big premium for the PowerPC processor inside. The result was expensive-squared. Having perhaps learned its lesson, Xilinx may price the new chips within reach of mere mortal designers. If the company could eke out a low-end version for under $10, I think it could be a big hit. 

(Quick lesson on chip pricing, by the way: it has nothing to do with the cost of making silicon. The ingredients in an FPGA or CPU chip are nearly free, but the production line needs to be kept working at full capacity. Bottom line: popularity is the biggest determinant of a chip’s price.)

Third, there’s the CPU-to-FPGA interconnect. Unless you do this properly, there’s no good reason to glue an FPGA and a CPU together in the first place; they might as well be separate chips. With a claimed 2500–3000 interconnects between the ARM processors and the FPGA fabric, it looks like Xilinx has this figured out.

Fourth, there are the peripherals. It’s all well and good to have your CPU and FPGA cohabitating, but you also need I/O. Unless you can put that I/O in the FPGA – and make it play nice with the processor – you’re wasting space. That, in turn, means Xilinx needs to provide lots of canned I/O IP and allow users to create more of their own. The company’s gained ten years of additional experience on this front, so I’m optimistic.

And finally, there are the tools. Xilinx’s first attempt at this was an FPGA with a processor inside. This time around, it’s a processor with an FPGA grafted on. That’s not just semantic hair-splitting: it’s the big difference between these chips and the old ones. The new chips will boot up and run just like normal microprocessors, meaning there’s no FPGA configuration required at all. You can simply ignore all that expensive FPGA fabric surrounding the pair of big Cortex-A9s – and you probably will during early debug sessions.

To me, that’s the key difference. Xilinx’s new chips will look, act, walk, and talk like real microprocessors. You’ll create and debug code for them like any other standalone CPU. Their FPGA-ishness can be ignored until you’re good and ready to start configuring it, and even then it won’t conflict (we’re told) with the microprocessor subsystem. Of course, I’m sure it’s possible to screw up your chip by mis-configuring the FPGA fabric, but at least then it will be your own fault and not some fundamental weakness of the chips themselves.

Even Xilinx can’t fix that problem. 

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