Articles – Page 249

November 15, 2011

When we hear the term “supercomputing,” each of us probably forms a different image in our head – depending on our age. For my generation, I like to visualize the semi-cylindrical form of the Cray-2, with its radical architecture and Flourinert cooling. It looked fast just sitting there. Others may envision anything from IBM mainframes to racks of blades to modern video gaming consoles.

In practical terms, supercomputing seems to mean computers that have a processing power equivalent to the smartphones of five years from now, at a cost premium of hundreds to thousands of times … Read More → "Supercomputing"

Gate First vs. Last

A Summary of the Issue Now That Things Should Have Settled Down

by Bryon Moyer

November 14, 2011

There’s been a war out there, and it goes something like this:

“It can’t be done the old way anymore. We need to use the new way.”

“No, actually, we will be able to do it the old way.”

“No you can’t; it won’t be reliable.”

“Yeah, we can, and we already did, and it works.”

“Hmmmph…”

And what might this issue be? It’s something that ought to be so arcane as to be of no interest whatsoever to anyone who has … Read More → "Gate First vs. Last"

Improving Embedded Software Integration

Combining Emulation and Offline Debugging

by Bryon Moyer

November 10, 2011

Today’s system-on-chip (SoC) designs are increasingly dependent on firmware and device drivers given the challenges of controlling various components (including the microcontroller, microprocessor or DSP cores, peripherals and interfaces). Accordingly, leading semiconductor companies are working to integrate software development and validation with silicon design and verification. One obstacle to such integration is the difficulty in effectively debugging early-stage embedded software. In this article we describe a way around this obstacle by way of a new software debugging methodology for software and system-level integration. When combined with traditional hardware emulation, the methodology reduces debug closure time and effort … Read More → "Improving Embedded Software Integration"

What Happens When Your GPS Fails?

by Dick Selwood

November 9, 2011

You are in the middle of nowhere when your GPS navigation system fails. Of course you no longer have a map in the car. No problem – make a cell-phone call asking for directions. The cell-phone isn’t working either. Is this the start of an alien invasion? Is the world about to end? No, it is the consequence of a minor failure in the satellites that provide the data for your in-car navigation system. These satellites also provide the timing information that co-ordinates the cell-phone base stations. So two separate systems are both affected by the same … Read More → "What Happens When Your GPS Fails?"

Black Helicopters

The Conspirator, the Victim, and the Flimflam Man

by Kevin Morris

November 8, 2011

John (a real engineer, but not his real name) sat in his office staring at his workstation monitor. John’s door was closed. It was always closed.

The software company where John and I worked was founded with a great deal of respect for engineering talent. We understood what many companies in our industry did not – that the biggest asset of any technology company is its people. Our campus was designed with that principle in mind. We provided real offices for all of our engineers – with real walls and real wooden doors that locked. Most of … Read More → "Black Helicopters"

Tips and Techniques for 28-nm Design Optimization

by Bryon Moyer

November 7, 2011

The tools available in Altera’s Quartus® II development software are designed to help address the challenges that effect timing closure—the availability of critical resources, the amount of routing congestion both local and global, and the ability to accurately time the logic to avoid timing volitions that could otherwise be caused by skews within the clock network—but often simple HDL changes will go a long way towards resolving timing issues and reducing the time it takes to achieve timing closure. This white paper addresses these possible … Read More → "Tips and Techniques for 28-nm Design Optimization"

System-Level Debugging and Monitoring of FPGA Designs

by Bryon Moyer

November 7, 2011

This white paper describes the latest state-of-the-art methods for debugging and monitoring large FPGA designs both during the simulation phase of development and after device configuration, and details the current practices that Altera has identified across a representative number of customer designs. In addition, the paper presents a platform that enables FPGA designers to easily add runtime visibility into their FPGA systems while ensuring the scalability needed in today’s increasingly large designs and compilation times.

… Read More →

Building a Custom Verification GUI with System Console

by Bryon Moyer

November 7, 2011

Want to know how to easily create GUI dashboards to interact with your design? Watch this new demo to learn how to:

Add run-time visibility into your FPGA systems
Access available run-time information using Tcl, a flexible command language
Create your own custom verification tool using graphical elements such as buttons, dials, and graphs
Develop solutions ranging from simple scripts to sophisticated GUI … Read More → "Building a Custom Verification GUI with System Console"

There Goes the Neighborhood

Zuken Redesigns their Board Tools from Scratch

by Bryon Moyer

November 7, 2011

Anyone who’s ever done any serious remodeling of their home knows the big decision. At some point, wouldn’t it really be easier just to mow down the existing structure and start over?

Little by little, as you add new ideas – “while you guys are at it” – the costs mount, and that’s even without considering the surprises that are inevitably encountered. And if you go from a two-dimensional home – one story – and add a third dimension, it gets crazier. Most single-story homes aren’t built … Read More → "There Goes the Neighborhood"

Optimize Your 28-nm FPGA Design for Maximum Performance

by Bryon Moyer

November 7, 2011

Want the best performance from your 28-nm FPGA design? Find out how you can make optimal use of Altera’s 28-nm architecture to maximize your system performance.

Watch this 10-minute webcast to learn about:

Our 28-nm architecture innovations
Recommended design optimization techniques
Quartus^® II software automated optimization tool

Read More → "Optimize Your 28-nm FPGA Design for Maximum Performance"