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MIPS Rolls Out Its First RISC-V Processor Core – It’s a Big ‘Un

Even though the company had telegraphed its big move, MIPS’s adoption of the RISC-V ISA for its future processor cores hit me like a ton of bricks. MIPS is one of the heroes of the early RISC revolution, and the company has gone through a lot of ups and downs. Big ups. Big downs. Jim Turley discussed the MIPS announcement about joining the RISC-V gang last year. (See “Wait, What? MIPS Becomes RISC-V.”) Last month at the RISC-V Summit, MIPS rolled out its first RISC-V core – the eVocore P8700 – an OOO (out of order) execution, multithreaded, 64-bit processor core designed for servers. The P8700 core will scale to 64 clusters with 512 processor cores in total, supporting 1024 harts (RISC-V hardware threads). In addition, MIPS announced its first P8700 customer, autonomous vehicle (AV) computer maker Mobileye.

The Mobileye announcement isn’t all that surprising because Mobileye has been using MIPS CPU cores in its AV SoCs for a decade. With the new P8700 core, Mobileye gets an OOO execution speed boost, growing ecosystem support for RISC-V processor cores, an established and growing software and development tool library, and a growing army of knowledgeable programmers who are familiar with the architecture, having likely learned about the RISC-V architecture in college. In addition, the switch means that Mobileye’s SoCs are no longer chained to a proprietary microprocessor architecture available from a single supplier. The company now finds itself awash in a rising sea of RISC-V processor core vendors. In fact, that’s one of the biggest advantages that RISC-V offers: core vendor choice.

The MIPS saga began 40 years ago at Stanford University. John Hennessy and his graduate students caught wind of John Cocke’s work at IBM on the 801 processor, which started in 1974. Back then, the Bell System needed an electronic telephone switch that could connect 300 calls per second. Figuring about 20,000 instructions per call setup and some overhead, the requirements called for a machine that could execute 12 million instructions per second (MIPS). That was about four times faster than IBM’s fastest mainframe at the time, a System/370 Model 168.

Cocke proposed building a hot rod processor, much in the same way that car enthusiasts turned old 1930s automobiles into fast cars: ditch the weight and put in a big engine. Instead of cutting off fenders and pulling off the hood to reduce weight, IBM’s 801 team ditched floating-point instructions, all memory-referencing instructions except for load and store, and, most especially, microcode. They built a big, pipelined execution engine out of pure hardware and created a board-level processor that hit 15 MIPS built out of Motorola MECL 10K small-scale logic chips. That execution rate exceeded the speed of IBM’s System/370 Model 168 by 5X. (IBM first experimented with instruction pipelining with the Model 7030 Stretch mainframe computer, delivered to the Los Alamos National Laboratory in 1961.)

The superlative results of the IBM 801 project lit a fuse and ignited a worldwide explosion in processor design that was based on a volatile gunpowder mixture that combined advancing VLSI semiconductor processes, standard-cell VLSI design as espoused by Professor Carver Mead at the California Institute of Technology (Caltech) and Lynn Conway at the Xerox Palo Alto Research Center (PARC), the UNIX operating system coming out of Bell Labs, and radical new optimizing compiler technology that could effectively harness the architectural innovations of RISC microprocessor hardware including:

  • Simple machine instructions
  • Large register files
  • Load/store architectures that rely heavily on fast access to those large register files and local memory caches
  • Pipelined hardware execution engines that execute one simple RISC machine instruction every clock cycle

Three of the microprocessor development projects that emerged from this explosion would become huge commercial successes and would have a profound effect on the future of microprocessor design and the microprocessor industry. Those three projects were the MIPS (Microprocessor without Interlocked Pipelined Stages) project led by Professor John Hennessy at Stanford University, the Berkeley RISC project led by Professor David Patterson at the University of California at Berkeley, which would become the basis for the SPARC architecture, and the ARM (Acorn RISC Machine) project led by Steve Furber and Sophie Wilson at Acorn Computers in the UK. Many more successful RISC architectures would soon emerge. The MIPS and SPARC processors would become central to workstation development in the 1980s. The ARM microprocessor took RISC architecture into the embedded world, and Arm’s progeny now reside inside nearly every mobile phone on the planet. However, this article is about MIPS.

Hennessy started talking with Skip Stritter, who worked on the Motorola 68000 microprocessor, and John Moussouris, who had worked on RISC processor design at IBM’s research labs in Yorktown Heights, NY. In 1984, the three met regularly over breakfast to discuss the possibility of starting a new company focused on developing high-performance microprocessors and computers based on Hennessy’s MIPS RISC project at Stanford. They founded MIPS Computer Systems that same year with venture capital money.

MIPS (the company) produced the R2000, its first microprocessor, in 1986, and immediately started selling it to minicomputer and workstation companies. Minicomputer pioneers like Digital Equipment Corporation (DEC) and Prime Computer adopted the R2000 to make the transition to microcomputers and microprocessor-based workstations, but they’d waited too long. Both companies are now long gone.

However, the R2000 and its successors became fundamental to the success of workstation companies including Silicon Graphics (SGI). In fact, MIPS RISC processors became so integral to SGI’s workstations that SGI acquired MIPS in 1992 and renamed it MIPS Technologies. During its time within SGI, MIPS continued to churn out bigger, better, and faster RISC processors including the two-chip R8000 superscalar microprocessor and R8010 floating-point unit that implemented floating-point instructions and limited OOO execution, the superscalar R10000 that implemented register renaming and full OOO execution, and the R12000.

However, by the end of the 1990s, SGI decided to go another way, so it spun out MIPS on June 20, 2000, before the R12000 work was completed. SGI continued to develop the R12000 and follow-on MIPS workstation-class processors while the newly spun-out MIPS Technologies focused on embedded RISC microprocessor cores, a market where Arm’s dominance was large and growing.

By 2008, the company’s fortunes were falling. In 2012, MIPS sold 498 of its 580 patents to Bridge Crossing, an IP acquisition vehicle of the patent-mitigation company named Allied Security Trust, a not-for-profit collective that protects its members against litigation from “patent assertion entities” (aka patent trolls). At the same time, IP vendor Imagination Technologies bought the other chunk of the company’s assets and its ongoing operations. Imagination Technologies sold what was left of the MIPS processor business to Tallwood Venture Capital in 2017, which in turn sold the business to an AI startup named Wave Computing the following year. Wave Computing declared bankruptcy in 2020 and then emerged from bankruptcy a year later while renaming itself MIPS – just MIPS this time. That same year, the newly reconstituted MIPS joined RISC-V International.

So, MIPS emerged from the wreckage of its complicated past with a clear mission that returns the company to its roots, developing high-end and mid-range processor cores, while using the deep institutional knowledge gleaned from nearly 40 years of high-end workstation processor development. The adoption of the RISC-V architecture allows MIPS to focus on processor core development while relying on the international RISC-V community to develop software and development tools. The MIPS eVocore P8700 processor core is the first such IP core and will be followed by an in-order-execution version of the same processor, called the P8500, later this year.

For now, MIPS will not be competing in the simpler embedded market. Although the company will continue to offer cores based on the earlier MIPS cores, development on the original MIPS RISC architectures has come to an end. The company has plenty of institutional knowledge from the R8000, R10000, and R12000 cores to move forward in the high-end RISC-V market. Meanwhile, MIPS has proven itself to be a survivor, and its alignment with the global RISC-V gang likely ensures that the company will continue to survive in this new ecosystem. 

References

MIPS Oral History Panel, Session 1: Founding the Company,” Computer History Museum, February 18, 2011

MIPS Oral History Panel, Session 2: Building the Company,” Computer History Museum, February 18, 2011

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