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Making FPGA SoC Easier

Lattice Propel Lowers the Bar

There are about a zillion SoCs on the market today, perhaps even a zillion and a half, we haven’t counted in awhile. Of course most of them are built on various forms of ARM MCUs or applications processors, and the line card includes a zillion squared permutations with various collections of peripherals and interfaces parked alongside the processor. It can be a dizzying experience to design a system around one, tediously comparing what’s on the chip to what you think you’ll need.

But, if you take the time to look through all those, you’ll generally find one that almost works for your application. It’ll be really nearly just about kinda perfect except for that one missing thing that totally disqualifies it. Then, you’ll look some more and find one that has absolutely everything you want, as well as a ton of extra stuff that costs you money and power and has no purpose in your application. Finally, you’ll pick one and design it in – only to find out your requirements changed mid-project and now you need to add an FPGA to the board to give you that one extra interface, accelerate an algorithm, or connect peg A to slot B.

So, here we go down the FPGA path. 

What if we’d started there in the first place? After all, you can build your own SoC with an FPGA and put exactly the peripherals and interfaces and accelerators you need. Then, in a couple months when your requirements change, you can add/change/modify them without having to re-design your board or your whole system. This is not new advice, of course. FPGAs have been replacing SoCs for awhile now, but most teams are intimidated by the hardware design talent required to get the FPGA-based SoC up and running. The lure of the pre-designed, pre-tested off-the-shelf SoC is intoxicating, and all seems well until that day when you find out you’re going down the FPGA road anyway. 

FPGA companies recognize this, of course, and go to great lengths to lower the barriers to entry in FPGA design. Lattice Semiconductor just released “Propel” – a new suite of tools and IP that makes creating a customized SoC on their FPGAs drag-and-drop simple. With a few clicks-and-drags, just about anybody can design their own custom SoC with a RISC-V processing subsystem – without having to dive into details of RTL design, synthesis, place-and-route, timing closure, and the other real and imagined horrors of FPGA design. 

For a long time, putting processors in small FPGAs was uncommon, and frankly challenging because the processor took such a large percentage of the available FPGA fabric to create what would end up being a pretty expensive, poor-performing processor. Small FPGAs usually just functioned as “glue logic,” bridging standards between various devices, adding IO to designs, even fixing logic bugs. But today’s small FPGAs are close in capability to mid-range and even large FPGAs of a few years ago, and with all the embedded applications that need the flexibility of FPGAs, the drive to add processors has become substantial. 

Propel is positioned nicely for teams that are doing embedded designs, have traditionally used off-the-shelf SoCs, need the flexibility of programmable logic in their system, but don’t have an established team of FPGA experts ready to take on the challenge. Propel has two major components, the Lattice Propel Builder, which is a set of graphical and command line IP integration tools that make configuring your processing subsystem a snap, and Lattice Propel SDK – which (as the name implies) is a software development environment that facilitates building, compiling, analyzing, and debugging software for the Lattice platform. The SDK includes software libraries and board support packages. 

Lattice was very early to the RISC-V party, and that decision seems to be paying off as RISC-V has gained tremendous momentum since Lattice first embraced it. The RISC-V ecosystem has grown exponentially, and having RISC-V at the core of the Propel offering is a solid choice that should do well for customers. RISC-V is actually an open ISA, rather than a specific processor architecture, allowing users to customize their implementation to meet their needs while maintaining software portability via the ISA. That allows it to be a viable and often attractive fee-free alternative to ARM architectures in a variety of application types from low-power to high-performance.

Lattice Propel Builder takes care of the pin-to-pin connections for attaching the processor to busses and peripherals, and yields a “correct by construction” system via wizard-guided configuration and parameterization. The ease of configuration combine with a quick download and install (Lattice’s tool download is considerably smaller than other FPGA vendors’) to get you to “Hello World” on software running on your FPGA-based processor system in minutes. Lattice Propel Builder includes access to a regularly updated IP server. The server currently offers eight processor and peripheral IP cores, including a RISC-V RV32I compliant processor core, and Lattice says all the IP cores available through Lattice Propel Builder are compatible with the AMBA on-chip interconnect specification.

Speaking of downloading software tools, there was a brief bit of controversy when Lattice first launched Propel. Savvy developers in the open source community noticed a new line in the software license limiting reverse-engineering bitstreams. Lattice was quick to respond, and posted the following: 

To the open source community, thank-you for pointing out a new bitstream usage restriction in the Lattice Propel license. We are excited about the community’s engagement with Lattice devices and our intent is to not hinder the creation of innovative open source FPGA tools.

You can log into the Lattice website and check out the updated license text at https://lnkd.in/gUr6NMa. Please note that the license text is also replicated during install, and the new text will be available in tools available for download early next week. Thanks again for the feedback.

Propel is available for download now, and will first support the Lattice MachXO3D FPGA family, with support for other FPGA families expected to follow.

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