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Lattice announces CrossLinkU-NX FPGA with USB 3.2 to Unlock Video Applications

Lattice has marked some new territory in the low-end FPGA market with the CrossLinkU-NX FPGA. While AMD and Intel have signaled renewed interest in this market by previewing the future appearance of the low-end Spartan UltraScale+ and Agilex 3 families respectively, Lattice has been busy rolling out new members of its low-end CrossLink family. The latest addition, called the CrossLinkU-NX FPGA, specifically targets video applications for the industrial and automation markets, and, even more specifically, targets video applications that communicate to host processors on the edge via USB 3.2.

Like the other members of the CrossLink-NX family, Lattice’s CrossLinkU-NX FPGA is based on a 28nm FD-SOI process, which gives this FPGA family its low-power operating characteristics. However, the CrossLinkU-NX FPGA goes even further in the low-power department by adding a newly minted, hardened IP block that drops the FPGA’s power consumption down to below 126 microwatts when the device enters sleep mode. In a published example, Lattice showed an application where the FPGA drew 180 mW in operating mode, less than 126 microwatts in sleep mode, and an average of 30 milliwatts based on a 20% operating duty cycle, with the device in sleep mode roughly 80% of the time. Note that you shouldn’t expect to get an 80% power reduction for every application that uses sleep mode. Your design’s power consumption will necessarily vary depending on how much you pack into the CrossLinkU-NX FPGA’s 33K logic cells and 64 DSPs, the operational clock speed of your FPGA circuitry, and how much time your circuit spends operating versus how much time it sleeps. There are a lot of variables to account for when calculating average power consumption.

However, do not get the idea that the CrossLinkU-NX FPGA is a general-purpose FPGA. Sure, you can use it that way, but Lattice designed several features into the device for a very specific purpose, video bridging, as illustrated in the graphic below:

The Lattice CrossLinkU-NX FPGA incorporates a USB 3.2 Gen 1×1 port specifically for video-bridging and other sensor-bridge applications. Image credit: Lattice Semiconductor

 

Lattice noticed that design teams developing video cameras for the industrial and automation markets were often using existing members of the company’s CrossLink-NX FPGAs to serve as a bridge from a video imaging sensor to a specific type of interface: USB. As pictured in the top half of the above graphic, labeled “Before,” the CrossLink-NX FPGA interfaced to the imaging sensor and communicated with a USB bridge chip so that the finished camera could talk to industrial PCs and similar edge servers. Anyone familiar with the long history of FPGAs knows that when FPGA vendors spot application trends like this one, they are likely to design a new FPGA that absorbs the function of a companion chip, especially if several key customers all seem to be taking similar approaches. The philosophy here is, “Why shouldn’t we be realizing the revenue from the adjacent device?”

That’s a game that the FPGA vendors have been playing for more than two decades now, and that’s exactly what’s happened in the case of the CrossLinkU-NX. It’s absorbed the USB bridge chip as illustrated by the lower half of the above graphic, labeled “Now.” The CrossLinkU-NX FPGA incorporates a hard IP block with a USB 3.2 Gen 1×1 interface capable of operating at 5 Gbps. This IP block will also operate as a USB 2.0 port at 480 Mbps for more generalized sensor-bridging applications, as shown in the figure below.

The Lattice CrossLinkU-NX FPGA can operate as a USB 3.2 Gen 1×1 device or as a USB 2.0 device and supports multiple types of I/O used by a wide range of sensors. Image credit: Lattice Semiconductor

On the sensor side, the CrossLinkU-NX FPGA explicitly supports the MIPI CSI-2 interface for imaging sensors. This FPGA has hardened transceivers for the MIPI D-PHY interface and requires an additional 1300 LUTs to instantiate a controller and complete a 4-lane MIPI D-PHY interface capable of operating at 4.8 Gbps. The CrossLinkU-NX FPGA also includes the usual cast of slower standard interfaces including I2C, I3C, SPI, QSPI, and GPIO. However, as you can see from the diagrams in the above figure, Lattice clearly believes that the primary target application for this FPGA will center around interfacing a video imaging sensor to a PC or some other sort of host processor through a USB connection. That’s not to say that you cannot drop a soft-core processor like a RISC-V core to perform some on-FPGA processing, as shown in the above figure. However, as I’ve written before, that seems like an inefficient use of some portion of the FPGA’s 33K logic cells. FPGA fabrics are not very efficient when used to build RISC microprocessors.

The figure below provides an overview of the resources available on the CrossLinkU-NX FPGA.

Hardened IP resources on the CrossLinkU-NX FPGA include a USB 32 Gen 1×1 interface, the “Always-On/Instant-On” sleep block for a low-power sleep mode, and a security block with AES256 and ECC256 accelerators. Image credit: Lattice Semiconductor 

Developers using the Lattice CrossLinkU-NX FPGA can take advantage of existing development software and soft IP available for the company’s CrossLink FPGA family, including the SensAI Stack. IP cores in the SensAI stack include convolutional neural network (CNN) and advanced CNN accelerators. The SensAI Stack also includes several video-related reference designs that know to work with CrossLink-NX FPGAs including:

  •         Object classification
  •         Hand gesture detection
  •         Barcode detection
  •         Key phrase detection
  •         Human face identification

Lattice has made major gains in market share in the low end of the FPGA market, and the announcement of the CrossLinkU-NX FPGA is a signal that the company intends to maintain the momentum it’s gained at the expense of its main FPGA competitors: AMD and Intel. Those two FPGA vendors seem to have recently awakened to Lattice’s growing encroachment into low-end territory, and both companies have recently announced plans to update their years- and decades-old low-end FPGA families. AMD announced the low-end Spartan UltraScale+ FPGA family last June, and Intel announced the low-end Agilex 3 family in September, just before its FPGA Technology Day event. However, unlike Lattice, which has provided detailed specifications for the CrossLinkU-NX FPGA, both AMD and Intel have been  remarkably tight-lipped about specifications for their upcoming Spartan UltraScale+ and Agilex 3 FPGAs. The lack of technical information suggests that these parts should not be expected to appear in the short term. Meanwhile, Lattice says it has scheduled production for the CrossLinkU-NX FPGA for Q4 2023, which is right about now.

It’s gratifying to see things perking along in the low-end FPGA arena. We have Lattice to thank for keeping this segment alive and thriving. I certainly expect that the competition will get even more interesting when AMD and Intel decide to share more technical specifications for their new low-end FPGA families. Meanwhile, there’s Lattice to keep us amused.

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