Embedded FPGA (eFPGA) IP is not new. Several companies including Achronix, Efinix, Flex Logix, Menta, and QuickLogic have been offering FPGA cores for integration into ASICs and SoCs for a while. ASIC designers use eFPGA cores to help future-proof their designs. The eFPGA can be used to patch bugs or add features as needed. These abilities help to avoid a costly and time-consuming re-spin of the ASIC. It’s a difficult bit of IP business with a limited market, chiefly used by semiconductor developers in the defense and aerospace segments. Analog Devices (ADI) bought all of Flex Logix’s technology assets and hired its technical team last November, cutting loose the segment’s most flamboyant player, Flex Logix founder and CEO Geoff Tate. It appears that ADI will only use the acquired eFPGA IP internally. However, the eFPGA IP segment now has a new player, Zero ASIC, already an established IP provider. Zero ASIC’s eFPGA IP product is named Platypus. The company’s new eFPGA offerings – including the IP core, the FPGA bitstream, and the tools – are made available as open standards.

Normally, I’d be writing some words to describe the situation. However, I’m going to quote directly from Zero ASIC’s Platypus press release because the company’s CEO, Andreas Olofsson, has done such a good job in summarizing the situation:

“Obsolescence is a critical issue for FPGA-based systems within aerospace, defense, healthcare, communications, automotive, and industrial applications, where lifespans range from 10 to 50 years. For instance, consider the development of the F-35 fighter jet, which began in 1997 and didn’t enter full production until 2021. During this period, transistor density increased by a factor of 10,000X, and the FPGA industry introduced six new generations of architectures.

“This mismatch between the relentless pace of semiconductor advancements and slow infrastructure development cycles has led to an estimated $50B–$70B in obsolescence-related NRE costs for the US military with 15% of all replacement semiconductor parts being counterfeit.”

These two paragraphs lay out the basic justification for eFPGA IP, which can help to make an ASIC or SoC design more resilient by adding some amount of programmability to the mix. However, the effectiveness of this programmability within a chip is entirely dependent on where the eFPGA block is placed in the chip’s architecture.

The press release continues:

“Since the inception of FPGAs in the 1980s, commercial FPGA products have become increasingly complex, less standardized, and more opaque, exacerbating issues related to parts obsolescence and counterfeiting. In the best case, an end-of-life notice for an FPGA device or eFPGA IP core necessitates a complete subsystem redesign. In the worst case, it may result in the termination of an entire program.”

This paragraph covers two major complaints often aimed at established FPGA chip vendors. First, they’ve focused on making increasingly complex FPGAs that are harder to use than previous devices. That’s the way of the world in all of semiconductors. It’s not unique to the FPGA segment. Second, end-of-life notices are a pain in the posterior no matter the segment. Again, it’s a way of life in the chip business. What this paragraph does not say is that FPGA players in general are good at maintaining the production of older products for decades, so the problem of FPGA chip obsolescence is largely confined to extremely long-lived designs, such as those found in fielded defense and aerospace projects like the F-35 fighter mentioned earlier in Zero ASIC’s press release, which continues:

“The logical next step in addressing the FPGA obsolescence and counterfeit problems is to move away from single source parts and establish a set of open-standard FPGA architectures, similar to the successful standards created for memory and passive components.”

This statement makes a huge leap of faith from problem statement to solution. It is Zero ASIC’s underlying premise for the Platypus eFPGA IP and associated tools, so let’s take a closer look at the offerings Zero ASIC has just announced followed by some Q&A with Olofsson.

As shown below in the Platypus block diagram, Zero ASIC’s eFPGA looks very much like any tiled FPGA, with tiles for logic, block RAM (BRAM), DSP, and I/O. There’s also the possibility for custom tiles within the FPGA array. That’s an advantage of an eFPGA not shared by standard FPGA chips.

A Zero ASIC Platypus eFPGA array consists of tiles for logic (CLB), block RAM (BRAM), DSP, and I/O, with an option for custom tiles. Image credit: Zero ASIC

Currently, Zero ASIC is offering one Platypus eFPGA array consisting of only CLB tiles, for a total of 2048 LUTs, with 1024 I/O tiles. The company is developing larger Platypus eFPGA arrays with as many as 131,072 LUTs and 8048 I/O tiles. These planned eFPGA arrays correspond to small and mid-range FPGA chips, but the advantage of an eFPGA is that it can be connected to the inner workings of an ASIC or SoC through thousands of on-chip connections, ensuring much faster data transfers within the system.

To date, the company has developed one eFPGA array, the experimental Z1010 heterogeneous eFPGA, with LUTs, DSPs, and BRAMs, which has been ported to the GlobalFoundries GF12LP manufacturing process. A photo of this experimental Z1010 array appears below. According to the company, “The official Z1010 standard eFPGA array will include a different ratio of LUTs, DSPs, and BRAM.”

Zero ASIC’s experimental Z1010 heterogeneous eFPGA includes tiles containing LUTs, DSPs, and BRAMs. It has been ported to the GlobalFoundries GF12LP manufacturing process. Image credit: Zero ASIC

Detailed descriptions of the various Platypus tiles are scant in the Zero ASIC Website. It appears that you can independently configure the number of LUTs per CLB, the number of inputs per LUT, and the number of routing channels among the tiles, which could make for some interesting optimizations that you cannot get with FPGA chips. Zero ASIC’s Website does not describe the capacities of the BRAM tiles or the makeup of the DSP tiles, so if you want those details, you’ll need to engage directly with the company.

Zero ASIC’s eFPGA offering also includes a tool called FPGA Architect, which is an EDA platform that generates correct-by-construction embedded FPGA cores. FPGA Architect automates the generation of:

•         Verilog RTL and netlists
•         Hardened array layout macros (DEF/GDS)
•         Architecture files for the company’s Logik EDA tools
•         Testing and integration infrastructure

Given the information in Zero ASIC’s press release, I asked Olofsson some questions about this offering. My questions and his responses appear below:

Steve Leibson: “The first question is about tools. Is Logik a Zero ASIC product? Someone else’s? I consider the tools to be equally important to the cores, so this is an important question for me.”

Andreas Olafsson: “Logik is a free and open-source FPGA toolchain developed by Zero ASIC. Essentially, it’s a free product, similar to GCC, Linux, Pytorch, LLVM, etc.  You can find all the sources here: Https://github.com/siliconcompiler/logik.

“Logik relies on a number of mature open-source components that have been developed over the years. In total, there is likely $20M+ of time and material invested in these open-source tools by some very smart people.

• High Level Synthesis (Bambu/Panda (Politecnico di Milano), 10+ years)
• Logical Synthesis (Yosus/ABC (Berkeley), 10+ years)
• Placement and routing (VPR (Toronto), 25 years))
• IP package management (SiliconCompiler, 4 years)

“VPR and ABC are the backbone of multiple commercial toolchains, but vendors don’t disclose it publicly.”

Steve Leibson: “I assume you’re aware that other FPGA IP vendors like Flex Logix and Menta are not setting the world on fire. Jeff Tate now lists his job as “Self Employed” on LinkedIn after selling off his FPGA IP company (Flex Logix). I’m interested in why Zero ASIC thinks things will be different for its FPGA IP offering. It’s a bit like Bullwinkle on the “Rocky and Bullwinkle Show” saying “This time, for sure!” or Charlie Brown taking another kick at the football held by Lucy van Pelt and, as always, whiffing the kick and ending up flat on his back.”

Andreas Olofsson: “The eFPGA IP market is a niche market, so it’s not easy. IP is really hard, with only a few vendors doing well. Being a subset of that market with a high sales threshold, the eFPGA market is near impossible.

“That being said, Zero ASIC is the first company to try the open architecture approach. We are licensing our hard IP cores but allow anyone who wants to clone the architecture/bitstream to do so for free including our customers. This means that the customer will never be left stranded with a dead architecture (eg. if the company is sold or goes out of business).

“We are not going to be competing with Xilinx/Altera on raw LUTs or toolchain/IP feature richness anytime soon. Our success hinges on a few factors:

• The customer must appreciate our open approach. If they favor PPA [power, performance, and area] over openness, then we still have work to do compared to our competition.
• The eFPGA market itself (how many customers can do something useful with a 2K to 100K LUT core?)
• Customers accept our Python based tool chain (no GUI, no TCL) and find it “good enough.”

“I hope we can agree that RISC-V has made a huge difference in the CPU space. RISC-V succeeded because the market wanted openness. We will find out if the same can be said for FPGAs.

“Final note: Eventually our open eFPGA cores will be made available as standardized chiplets (2mm x 2mm, 4.1mm x 4.1mm) as well.”

So, there are the details of Zero ASIC’s eFPGA offering. Perhaps it’s what you need for your next ASIC or SoC design. Andreas Olafsson is betting that it is.