feature article
Subscribe Now

Intel’s “World’s Largest” FPGA

The New Stratix 10 GX 10M

All this has happened before, and all this will happen again
— J.M. Barrie – Peter Pan
— Battlestar Galactica

First, let’s get the headline out there. Intel now boasts the world’s largest FPGA – the Stratix 10 GX 10M. As one might guess from the title, this new FPGA packs a whopping 10.2 million logic elements. This is fantastic news for those who want the most possible programmable logic in one package. Those doing FPGA-based prototyping and emulation should be particularly excited with this level of integration. 

The Stratix 10 GX 10M uses Intel’s EMIB (Embedded Multi-die Interconnect Bridge) technology to combine two large FPGA chips in a single package, yielding an FPGA with 10.2 million “logic elements” (we’ll explain why that’s in quotes in a bit) fabricated from a staggering 43.3 billion transistors. One of the first questions that might come to mind is “How are two chips in a single package different or better than simply using two FPGAs on a board?” Glad you asked. Using multi-die packaging technology like EMIB, we can create dramatically more connections between chips than we can by using conventional IO routed through pins and PCBs, and these connections are faster, shorter, and consume less power. Intel says that the EMIB passes through “up to 25,290 connections” between chips – an order of magnitude more than we could get through conventional IO. 

Stratix 10 GX 10M also packs in 308 Mbits of memory, 6,912 DSP blocks with 18×19 multipliers, 48 SerDes transceivers operating at up to 17.4 Gbps, and 2,304 external IO pins. If you’re prototyping large designs, that’s a tremendous pool of resources to use without having to partition across multiple FPGAs on a board. It simplifies the challenge of partitioning complex designs across FPGAs in a prototype and, in many cases, should eliminate it altogether. 

Prior to the Intel announcement, the largest FPGA was the Xilinx Virtex UltraScale+ VU19P, which was announced in August. That is a 16nm device with 35 billion transistors, consisting of four chips on an interposer, boasting 9 million logic cells. Prior to that, the largest FPGA was the Virtex UltraScale 440, with 5.5 million logic cells.

Here’s a tricky part, though. Xilinx’s VU19P was announced in August, but it won’t ship until an estimated Q1 2020. Intel’s new Stratix 10 GX 10M is shipping today. So, Xilinx announced their FPGA was the world’s largest, but by the time it’s actually shipping, it will be second place.

Why would all this back-and-forth marketing bluster matter, or even be interesting? All this has happened before, and it will all happen again. The rivalry between the two large FPGA companies is a semiconductor industry trope that has spanned decades. Marketing teams on both sides have hurled superlatives back and forth in press releases since, well, since the people writing them each worked for the other company, frankly. In the same way that professional athletes traded to another franchise go to work competing with their former teammates, marketers bounce back and forth between FPGA franchises lobbing rhetorical grenades across the same chasm, often defending against attacks they previously authored themselves. 

Back in 2005, we were inundated by superlative claims from the two FPGA vendors. Every week, it seemed, one was making a claim to be the fastest, biggest, lowest power, most flexible, transistor-y-est programmable logic device on the market, on Earth, in the Universe! One day we got a call from Altera (Yup, the same team that’s now at Intel) asking to brief us on their new “World’s Largest” FPGA. We wrote this piece in response: https://www.eejournal.com/article/20050510_worldsbest/

So, this year, when Intel called once again to tell us they wanted to brief us on their new World’s Largest FPGA, we couldn’t help but experience a bit of deja vu.  

This time, however, the world is a different place. In 2005, the largest FPGA consisted of fewer than 200,000 logic elements – not even the “.2” part of today’s 10.2 million LUT unit. In the “10M” part name, Intel rounded off more LUTs than the number in the entire “World’s Largest” FPGA they previously bragged about. 

And, before we forget, what are “logic elements” anyway? What exactly does this FPGA include 10.2 million of? With a little knowledge of FPGAs, one might guess that is the number of look-up-table (LUT) cells on the chip. It would make sense to measure the amount of FPGA logic by counting the cells, right?


In the old days, LUTs had four inputs. As FPGAs evolved, they expanded to six and even seven or eight inputs (depending on whose cell you’re looking at). Intel’s current cell is the “Adaptive Logic Module” or ALM. As Intel explains, “Each ALM contains a variety of LUT-based resources that can be divided between two combinational adaptive LUTs (ALUTs), a two-bits full adder, and four registers. With up to eight inputs for the two combinational ALUTs, one ALM can implement various combinations of two functions. This adaptability allows an ALM to be completely backward-compatible with four-input LUT architectures. One ALM can also implement a subset of eight-input functions.”

These devices contain 3,466,080 ALMs. By our math, that means that one ALM equals 2.94 “logic elements” You might, then, think that a “logic element” is roughly equivalent to one 4-input LUT, and that metric is used for historical reasons. Well – nope again. Back when 4-input LUTs were the norm, FPGA companies couldn’t agree just to count the LUTs either. Each company claimed that THEIR LUT4 cell was actually more powerful than the other’s, and therefore came up with other names like “logic elements” that were basically the number of cells multiplied by some factor that made them slightly larger than their competitor’s number.

Now is it clear? Nah, we didn’t think so.

It is also interesting to note that both Intel and Xilinx have built their largest FPGAs on their own previous-generation technology. While both companies are touting new devices fabricated on the latest 10/7nm process, the largest devices sold by both companies are on older process nodes – Intel’s Stratix 10 family and Xilinx’s Virtex UltraScale+. This gives us some insight into the challenges associated with finding niches where the latest process technology actually brings market value, and it is yet another sign that Moore’s Law is rapidly approaching bankruptcy.

Finally, we should mention that, while the prototyping and emulation market is important, and having the largest FPGA is certainly excellent fodder for bragging rights, the number of chips this size actually sold and installed will be surprisingly small. That means, of course, that the price tag will be staggering – but we don’t have that information yet. It will be interesting to watch.


One thought on “Intel’s “World’s Largest” FPGA”

  1. What a crock of crap! No,Virginia, Santa does not design electronics using logic elements. He uses Boolean Algebra! But even that is hidden/obfuscated by the idiots that believe if you hide the logic behind if/else syntax then any idiot can design a chip.

    Intel itself does not realize that the true dual port embedded RAM blocks and 6 input LUTs can be key to future chip design.

    The embedded memories are all over the chip so no reason to use flops and fabric to implement registers.

    And another important thing is that the C# AST SyntaxWalker will spit out the operands and operators in the correct sequence for evaluation for operator precedence and parentheses.

    One 6 input LUT per data width can implement an ALU to do 16 functions of 2 data bits. There are adders, multiplier, comparator blocks to do most of the heavy lifting.

    No, I do not know a way to count the imaginary logic elements. And frankly my dear…

Leave a Reply

featured blogs
Jan 21, 2021
'€œWhether we are based on carbon or on silicon makes no fundamental difference; we should each be treated with appropriate respect.'€ -- Arthur C. Clarke (2010: Odyssey Two)...
Jan 21, 2021
We have recently interviewed some of our EMEA team members to hear about their unique backgrounds and experiences shaping the future of technology with Cadence. For our second interview, we spoke... [[ Click on the title to access the full blog on the Cadence Community site....
Jan 20, 2021
Explore how EDA tools & proven IP accelerate the automotive design process and ensure compliance with Automotive Safety Integrity Levels & ISO requirements. The post How EDA Tools and IP Support Automotive Functional Safety Compliance appeared first on From Silicon...
Jan 19, 2021
I'€™ve been reading year-end and upcoming year lists about the future trends affecting technology and electronics. Topics run the gamut from expanding technologies like 5G, AI, electric vehicles, and various realities (XR, VR, MR), to external pressures like increased gover...

featured paper

Speeding Up Large-Scale EM Simulation of ICs Without Compromising Accuracy

Sponsored by Cadence Design Systems

With growing on-chip RF content, electromagnetic (EM) simulation of passives is critical — from selecting the right RF design candidates to detecting parasitic coupling. Being on-chip, accurate EM analysis requires a tie in to the process technology with process design kits (PDKs) and foundry-certified EM simulation technology. Anything short of that could compromise the RFIC’s functionality. Learn how to get the highest-in-class accuracy and 10X faster analysis.

Click here to download the whitepaper

featured chalk talk

TI Robotics System Learning Kit

Sponsored by Mouser Electronics and Texas Instruments

Robotics projects can get complicated quickly, and finding a set of components, controllers, networking, and software that plays nicely together is a real headache. In this episode of Chalk Talk, Amelia Dalton chats with Mark Easley of Texas Instruments aVBOUT THE TI-RSLK Robotics Kit, which will get you up and running on your next robotics project in no time.

Click here for more information about the Texas Instruments TIRSLK-EVM Robotics System Lab Kit