For decades, the idea of embedded FPGA fabric has been hanging around the industry like a comic sidekick – providing entertaining conversation, but never really taking part in the plot. The concept seemed solid enough on paper. Put some LUT fabric on your ASIC along with the other stuff and you get additional flexibility, maybe avoiding the almost-inevitable need to park an expensive FPGA right next to your ASIC when your chip lands on a board. LUTs are not rocket science, and adding some programmable logic to a design should be a pretty simple proposition – from a hardware design perspective, at least.
Unfortunately, actually making productive use of that embedded FPGA fabric was a much scarier proposition. The big FPGA companies have made an enormous investment in design tools that smoothly take your RTL and crunch it into a working bitstream that can program their devices. The companies who were offering embedded FPGA IP for ASIC design had minimal tools at best, and most chip design teams were highly reluctant to give up a bunch of silicon real estate on their device for something that might or might not be useful.
Now, all that seems to have changed. A number of companies have entered the eFPGA fray, and, from all appearances, the concept is getting traction. Every vendor we talked to reports major design wins, and a confluence of several technical and market factors seems to have suddenly paved the road for rapid growth in eFPGA adoption.
There are at least five vendors offering eFPGA technology at this point – Menta, Flex Logix, Achronix, QuickLogic, and ADICSYS. Interestingly, these companies cannot really be considered “competitors” with each other because each one (at this point) seems to be focusing on a particular market segment or application area. It would be surprising if there were many situations where a design team was evaluating more than one of these for a particular project.
Two of the current suppliers, Achronix and QuickLogic, also sell FPGAs. That means they both have years (or even decades) of development and experience supporting robust FPGA design tool suites. Both companies’ tool suites are well regarded by their FPGA customers, and that should carry over into their eFPGA offerings. The two companies’ target markets are at opposite ends of the spectrum, however.
Achronix is aiming at “high-performance, compute-intensive and real-time processing applications such as AI, machine learning, 5G wireless, networking, and automotive” with their Speedcore eFPGA IP. Achronix has a core generator that creates custom-configured IP blocks with the size and capabilities required for your application. Their ACE design tool suite is used to program the custom block. Achronix claims significant benefits for using embedded (versus stand-alone) FPGAs, with power savings (dynamic plus static) estimated at over 50%, latencies reduced by an order of magnitude, considerably lower system cost, and reduced board size and complexity. Most of these savings are a result of eliminating the 2 sets of high-speed IOs that are required to connect an ASIC/SoC to a conventional FPGA. Speedcore is available on TSMC 16FF+ and is in development on TSMC 7nm.
Achronix can build embedded arrays of “any size” that include your desired mix of blocks: logic blocks with 4-input look-up-tables (LUTs), plus integrated wide mux functions and fast adders, logic RAM with up to 4 kb per memory block, block RAM with up to 20 kb per memory block, and DSP64 blocks, where each block has a 18 × 27 multiplier, 64-bit accumulator and 27-bit pre-adder. Obviously, you can build a substantial amount of accelerator or DSP capability on your chip with this technology. Achronix’s business has exploded in the past year since the announcement of Speedcore, and the company has locked in numerous design wins.
The QuickLogic ArcticPro eFPGA offering sits on the opposite end of the spectrum. Rather than the hundreds of thousands of LUTs possible with Achronix, QuickLogic offers embedded blocks in the 16×16 up to 64×64 LUT range. Targeting mobile/consumer-class designs, QuickLogic is aiming at IoT edge applications such as wearables, and their eFPGA is going for the attention of the microwatt crowd. QuickLogic supports the larger geometries popular in consumer-grade SoCs such as 65nm and 40nm processes from GLOBALFOUNDRIES and SMIC, and now they are designing for the 22nm process.
QuickLogic’s “Borealis Compiler” defines the size of the eFPGA array and generates the necessary files for SoC integration (.cdl, .v, .lib, .lef and .gds). Then the “Aurora” design tool suite handles the FPGA flow with Mentor’s Precision synthesis, QuickLogic’s Aurora place and route, and compatibility with industry-standard HDL simulators such as NC-Sim, VCS, Questa, or ModelSim.
Flex Logix features a novel interconnect architecture in their EFLX array IP, which the company claims is twice as dense as conventional FPGA fabric, using fewer metal layers. Flex Logix builds their EFLX arrays with tiles in two sizes – 150 LUTs (EFLX150) and 4K LUTs (EFLX4K). These can be used to build arrays from approximately 150 LUTs all the way up to 200K LUTs (50 tile array of EFLX4Ks) on a wide range of CMOS processes. Flex Logix also has a new, second-generation architecture with 6-input LUTs, MACs with 10-deep pipelines, and DFT enhancements. Their EFLX-2.5K and EFLX-100 cores are available in TSMC 16FFC/FF+/12FFC. Flex Logix “EFLX Compiler” converts RTL into bitstreams to program the embedded blocks. Flex Logix has logged numerous design wins (and announced additional ones just yesterday) – primarily in areas like data center acceleration, deep learning, application-specific IO configuration, and other acceleration, networking, and integration applications.
Menta eFPGAs are based on 6-input LUTs, and they are available on various CMOS processes, including TSMC 28HPM/HPC+, STM 28FDSOI, and GLOBALFOUNDRIES 32SOI and 14LPP. Menta offers a selection of pre-built IP cores that include five eFPGA options, ranging from 7k- to 60k-equivalent ASIC gates (256 – 2K LUT6 cells – which is roughly equivalent to 650 – 5K LUT4s), plus 18-bit MACs. The IP cores are delivered as hard macros with “optimized array sizes for the embedded Logic Blocks (eLB) and embedded Customer Blocks (eCB) to address various markets and applications.”
Menta has been around for over a decade and is on their fourth generation of eFPGA IP. Interestingly, Menta’s cells are based on DFF logic (rather than the conventional SRAM-style cell), which the company claims improves reliability and reduces single-event-upset (SEU) vulnerability. For testing, Menta has patented a technology based on multiplexed scan using a boundary scan isolation wrapper that offers a standard DFT approach.
ADICSYS offers what the company calls synthesizable programmable cores (SPC). The IP is delivered as standard RTL that is synthesized with the rest of your design. This approach should simplify the design flow somewhat, although there is likely some performance penalty versus pre-configured arrays or blocks such as those that the other vendors provide. ADICSYS says their IP can be used to generate arrays from 100 LUTs up to 100K LUTs. The company’s design flow is compatible with third-party synthesis and analysis tools, combined with a proprietary place-and-route engine. ADICSYS says that they have been in the production of customer silicon since 2012.
This abundance of options and rapid uptake of eFPGA technology in ASIC/SoC designs is a new threat to the dominance of stand-alone FPGAs from companies like Xilinx and Intel. Third-party SoCs with embedded fabric could compete with the two big players’ SoC FPGA offerings, and the addition of FPGA fabric to custom ASIC designs will undoubtedly eliminate some sockets that would have been otherwise taken by stand-alone FPGAs. The advantages of eFPGA in cost, power consumption, performance, and board complexity are substantial, and it will be interesting to see what kinds of applications become the “sweet spot” for eFPGA adoption.