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eASIC’s Big Win

Intel’s Acquisition Finds Its New Legs

Here at EE Journal world headquarters, we get a lot of press releases informing us that company A has made a deal with important customer B. Seriously. Many per day. Yawn. You may also notice the number of articles we typically do on those topics. Let’s count here… zero… uh, can we borrow from the tens place… no… yeah, zero. And yet, here we go talking about an announcement that is essentially that. eASIC – newly acquired by Intel and rolled into the (formerly Altera) programmable systems group (PSG) has won a deal with ZTE to do a cost reduction on previously FPGA-based 5G infrastructure gear using Intel/eASIC’s structured ASIC flow and technology. 

There you go! Thanks for reading.

And yet we continue…

Remember “structured ASIC”? Wow, there’s a flashback! Here’s a little reminder – back in the days well after 8-track tapes, but before the end of the MySpace craze, our industry flirted with a “technology” (mostly a marketing buzzword) called “structured ASIC.” If you’re feeling a little flushed right now, it’s OK. We fell for it, too. At that time, back in the two-thousand double-naughts, we had a publication called “FPGA Journal” that we temporarily re-named “FPGA and Structured ASIC Journal.” Yep, with stars in our eyes and that glossed-over look of people just inducted into a crazy religious cult, we added the extra words to our masthead and waited with giddy abandon for the magic of the next technological revolution. 

Luckily, we used pencil. 

Structured ASIC was really a rehash of the concept of gate arrays from the 1980s. The idea was that a chip could be partially fabricated in bulk, and then with a bit of elegant and fancy customization in a few metal layers, you could have your own custom ASIC for a small fraction of the design cost and schedule. Several big semiconductor companies rebranded themselves with structured ASIC in starring roles. The floodgates were opened and… the silence was deafening. Customers had absolutely no interest in structured ASIC. 

After a couple of years, everyone quietly removed “structured ASIC” from their logos, web pages, and marketing materials, and life drifted back to normal. Nothing to see here. Move on along. However, one small semiconductor company persisted with the structured ASIC idea and trudged right along, developing improved ways to implement the concept and deliver on the promise of low NREs, fast design turnaround, and better power, speed, and unit cost numbers than FPGAs. It turns out that some customers saw compelling benefits in the idea, and eASIC did a nice, steady, growing business delivering structured ASICs to happy customers. They also probably still wore parachute pants.

The cool thing about structured ASIC as implemented by eASIC is the smooth transition from an FPGA design to a functionally equivalent ASIC. Since FPGAs are known throughout the land as the time-to-market fast-prototyping champions, a substantial percentage of the FPGA chips sold have been in rapidly evolving application areas where unit cost and power consumption are less important than getting your box in customers hands right now – instead of 12 to 18 months from now. This is critical with technologies such as 5G, for example, where putting working gear into customers’ hands is vastly more valuable than cutting big swaths out of the BOM cost. 

But, once that early market frenzy begins to wane, those big, expensive, power-hungry FPGAs become a liability. What then? It would be premature to start developing a full-blown ASIC before the technology and standards stabilize. That’s one of the big reasons for using FPGAs in the first place. Once the technology does stabilize, however, the race is on once again. The first company to deliver cost-reduced, speed- and power-optimized non-FPGA versions of their gear to market will capture the high-margin, high-volume sweet spot of the mass adoption cycle.  

There are very big bucks at stake.

If you start developing a conventional ASIC on day zero of stable technology standards and specs, you’re a good two years from launching second-generation products. But, if you could just take your FPGA design and magically morph it into an ASIC with most of the benefits of a full-blown scratch ASIC design, you could beat all those conventional-ASIC folks by a meaningful margin. This appears to be what ZTE was thinking when they chose eASIC for their high-volume 5G wireless designs. It is interesting to see structured ASIC quietly move back onto the big-time stage after over a decade in relative hibernation. Perhaps the “Intel” moniker will make eASIC a more viable consideration for large-company high-stakes design sockets, and perhaps the smooth design flow from FPGA-centric prototype to ASIC-based production will capture the imaginations of increasing numbers of engineering teams. 

There are more interesting factors to consider here as well.

First, the attraction of FPGA technology is not limited to the ability to rapidly prototype. In some applications, the in-system reprogrammability of FPGAs is a first-order feature that persists long-term. Software-defined radio, for example, can make use of partial reconfiguration of FPGAs to hot-swap modems. Neural network inferencing can use FPGA logic to make their processing engines reprogrammable. The list goes on. So, ideally we could start a design with 100% FPGA in the prototyping stage and then harden the parts that we know aren’t going to change, using structured ASIC technology. This is the idea Intel apparently has with their recently-announced Agilex FPGA family, which allows for heterogeneous chiplets to be combined with FPGA fabric in the same package, using Intel’s EMIB 2.5D packaging interconnect. One could have the FPGA die in the same package with eASIC-ized chiplets for optimized portions of the design that don’t require FPGA-like programmability.

A second fun fact can be divined by looking at eASIC’s history. It turns out that the company has a robust design flow for converting designs from Xilinx FPGAs as well. This gives Intel a dangerous second shot at capturing the high-volume phase of a design, even if they lost out to Xilinx on the initial FPGA-based version. Engineering teams could presumably just bring in their Xilinx FPGA design and have it converted to eASIC structured ASIC for volume production. Ouch.

It will be interesting to watch how the one-two punch of FPGA followed by structured ASIC catches on. There are bound to be realities that make the process more complicated than it might initially seem. Back when they were Altera, Intel PSG had their own run at the structured ASIC game with a service called HardCopy that took FPGA designs into functionally-equivalent ASICs. For a variety of reasons, that effort did not perform well in the market. eASIC, however, seemed to find a formula that had legs and has endured in the structured ASIC world when just about all others have failed. Perhaps their magic will keep working, now that they are part of Intel?

4 thoughts on “eASIC’s Big Win”

  1. A good article, as usual at EE Journal.
    For the record, Altera’s HardCopy was very successful for several generations and with many key customers. I am sure that experience by Intel’s PSG led to the acquisition of eASIC.

  2. Would be nice to have your cake, and eat it too … err … to still have some reconfigurability after locking down a core part of a design, to pick up a little speed and lower power. Like only harden 1/2 the chip

    1. @TotallyLost – my understanding is you can kinda’ do that. With Agilex, you can have chiplets with parts of your design hardened via eASIC technology connected via EMIB with FPGA fabric.

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