Altera has carved a unique niche in the market with their HardCopy ASIC offering. As we all know, FPGAs offer some compelling benefits when compared with traditional ASICs – short design cycles, zero-NRE, and in-field re-programmability are the ones most often cited. For low- to medium-volume applications, FPGAs can be a wise choice compared with a high-risk, high-NRE, low-volume ASIC run.
FPGAs are not a panacea, however. Low-cost FPGAs don’t have the speed, capacity, or rich feature set of their high-end brethren. If you need advanced capabilities, you’ll pay an advanced price, and the economics of FPGA use change completely. There has long been a hole in the market for designs that require high-capacity, high-performance devices at moderate production levels, where FPGAs are too expensive on a unit cost basis and the high NRE costs of ASIC make amortizing that expense over a modest production run almost impossible.
This is where Altera’s HardCopy fits in. HardCopy is a process that takes a working FPGA design implemented in one of Altera’s high-end FPGAs (such as Stratix II) and gives you a functionally- and footprint-equivalent ASIC at a fraction of the unit cost. From your perspective, you design an FPGA, use that device in your prototypes, and then invest a modest NRE to get back an equivalent ASIC. This is most of the best of both worlds. While you still pay an NRE, the cost is significantly lower than a typical from-scratch ASIC design. You can prototype with the FPGA (and even potentially do early production) on the same board that the ASIC implementation will use. When you do get the ASIC, you should get an additional bonus of faster operating speeds, lower power consumption, and of course much lower unit cost.
Recently, Tektronix found themselves in exactly that situation. Tek was developing a line of new entry-level oscilloscopes – the MSO2000 (mixed signal) and the DPO2000 (Digital Phosphor Oscilloscope). These devices required ASIC-level performance and unit cost but with FPGA-esque NRE and design cycles. Accustomed to doing full-boat ASIC designs in their more expensive scopes, the team decided to give Altera’s HardCopy ASIC a try. The new scopes were bringing high-end features to the entry-level price point. With 1GS/s sample rates, 16 digital channels, and 5000 wfm/s waveform capture on a 200MHz scope, performance was critical. The team was integrating a large portion of the workload of the new scope into the HardCopy device, including embedded processing with Altera’s Nios II soft-core RISC processor.
The HardCopy device is the main digital processing system for the scope – signals go from the analog-to-digital converter directly to this chip. The HardCopy device stores the data into DRAM and does all of the processing required to make pictures of the waveforms – including driving the LCD display. A companion processor handles the application and UI-level functions and software while the Nios-II processor on the HardCopy device manages all the real-time functions.
The first step in the Tek team’s development process was to realize their design in a Stratix II 90nm FPGA. With an ASIC background, the team didn’t want to cut any corners on their first HardCopy design. “We didn’t want to change our process flow from ASIC,” said Paul Gerlach, Principal Engineer with Tektronix. “We gave the same amount of attention we always have to timing closure, constraint reviews, and everything else we’d do in designing an ASIC.”
The ASIC approach served the team well, and soon they had prototype systems with Stratix II FPGAs for their software team to use. “We brought in the software developers much earlier than usual,” Gerlach continues. “This improved our product quality. The prototype gave us significantly more verification coverage – not just more clock cycles, but the software developers gave us a lot of actual use exactly like the final product.”
The HardCopy design flow doesn’t require a re-design from the FPGA to the ASIC versions. The HardCopy ASIC is essentially an FPGA with the configuration logic “hardened.” SRAM-based configuration cells are replaced with metal-to-metal connections, reducing the die size, increasing performance, and reducing power consumption – particularly static power. Once Tektronix had the design up and running on the FPGA, working products could be constructed exactly like the final versions, only with FPGAs where the HardCopy ASIC would eventually sit. These prototype devices were used by beta customers to provide critical feedback on the design even before the ASIC went to tapeout.
“We knew that the ASIC device would have better performance and power consumption than the FPGA, but we didn’t want to bet on that,” Gerlach explains. “Early on, we made a decision to design only to the capabilities of the FPGA. That meant our [FPGA-based] prototypes could run at-speed with no design changes later on.”
It is possible that power supply design could be scaled back with the ASIC version if real-world power consumption for the system proves to be significantly lower than expected. However, having a fully-functional, full-speed prototype allowed beta customers and QA engineers to experience the final-product capabilities during verification and evaluation. “We ended up finding a bug at the last minute and correcting it before tapeout,” Gerlach recalls. “That might make it sound like the prototyping process didn’t work, but in fact it proves that it did. We asked the software team for one final list of anything suspicious they’d noticed during the development process. One developer sent us an e-mail about a problem he remembered another developer noticing… It ended up exposing a heinous race condition that we never could have caught with conventional verification techniques. We had to put in a couple of extra days over the final weekend, but it ended up saving us an ASIC re-spin.”
Other design teams we’ve talked to that have used HardCopy have described an iterative design flow where many versions of the FPGA design were deployed in prototypes, each time capturing customer feedback, making design changes, and updating the prototypes. This iterative, evolutionary design validation and qualification process with FPGA-based prototypes brings a new design flow to the table for creating solid ASIC designs on the first try. In addition, the design and verification steps that are not required for HardCopy can significantly shorten the design flow compared with a normal ASIC design. Tektronix reported an approximate 20% design cycle savings from their use of HardCopy.
The matched pair of Stratix and HardCopy (each of the past several generations of Altera high-end FPGAs has had a HardCopy ASIC counterpart) represents a unique solution in the custom logic space that we expect will continue to grow in importance. The combination provides significant value in the gap between high-volume, low-cost FPGAs and lower-cost ASIC technologies. With more design teams like this one at Tektronix validating the methodology by bringing it into mainstream design projects, we can expect to see a lot more activity on this kind of FPGA-to-ASIC product development.