feature article
Subscribe Now

ARM Announces Names and Claims

Upcoming CPU, GPU Cores Have Names, but No Technical Details

In its latest gender reveal party, ARM today announced the names of its next generation of IP cores and… not much else. There weren’t even any fireworks, drunkenness, injuries, or YouTube-worthy stunts. 

The company did roll out two new buzz phrases, though: “total compute” and “purpose-built compute,” by which it means there’s a processor, coprocessor, GPU, or system bus for every conceivable purpose. It’s a reminder that you can pretty much build anything you want using naught but IP cores licensed from the British/Japanese/maybe American company. 

For the silicon genealogists filling out the ARM family tree, the names of the new offspring will be (in no particular order) Cortex-X2, Cortex-A710, Cortex-A510, Mali-G710, Mali-G510, Mali-G310, CoreLink CI-700, and CoreLink NI-700. The three Cortex CPUs will be the first based on the new ARMv9 architecture specification

The good news is that each new CPU, GPU, and interface will be – surprise! – faster and better than its predecessor. Cortex-X2 is expected to be 16% faster than an X1 running at the same frequency. That’s an oddly specific number, given that no explanation was given for the improvement. When questioned on how ARM arrived at that number or how it was achieved, Director of Product Management Aditya Bedi basically replied that they tried really hard. Ooookay

Similarly, the new Cortex-A710 is purported to be 10% quicker than the existing A78, and the Cortex-A510 will boast a substantial 35% “performance uplift” versus the A55. 

Footnotes provided afterwards offered some clarification. In all three cases, performance numbers refer to simulated SPECint_base2006 scores, and assume that the old and new cores are running at the same frequency. They also stipulate that the newer CPUs all get twice the L3 cache of their older siblings. Odd. It’s possible that the Cortex-X2, 710, and 510 all require 2× larger caches. Maybe that’s the minimum configuration. Or maybe the extra imaginary cache help polish the benchmark numbers. Too early to say. 

The A710 and A510 are designed to form a big.little pair, much as the A78 and A55 do now. ARM pointed out that the A510 is the company’s first new “little” processor design since the A55 came out four years ago. In contrast, the A78 and Cortex-X1 aren’t even out of diapers yet, both barely a year old. 

The idea is that you surround a Cortex-X2 with multiple A710 cores and partner those with multiple A510 cores to create a processing cluster that can run fast or slow, depending on workload. Now that ARM-based chips are appearing in mainstream laptops (for which read Apple MacBook), ARM is keen to make laptop-based performance comparisons. Sadly, that comparison amounted to, and I quote, “+40% peak single thread performance vs. 2020 mainstream laptop silicon.” 

Given that real chips based on the new Cortex-A710 and A510 won’t be available for many months, and laptops based on those chips are probably a year after that, we’re comparing a late-2022 computer against a “2020 mainstream” product. Not surprising that some future computer would be faster than one that’s two years older. When asked directly whether they had any PC-related benchmarks to share, ARM General Manager Paul Williamson said no. 

Turns out, the claim is based on a simulated shoot-out against Intel’s Core i5-1135G7. Trouble is, the Intel chip normally runs at 2.4 GHz, while ARM gave itself a simulated 3.5 GHz, a 45% faster clock rate for a 40% gain in performance. Worryingly, Intel specifies a 28W TDP for its device, but ARM stipulated just 15W TDP, blaming the unnamed laptop it used for this test. Reducing the thermal envelope by almost half might mean the processor has to be throttled back from its already slower frequency. Oh, and the Cortex-X2 gets another L3 cache boost, this time to 16MB, or double the x86 chip’s cache size and four times what it was in the previous simu-test. Can you say benchmarketing? 

And why the “peak” and “single thread” qualifiers? When two Cortex-A510 cores are twinned, they share a single vector unit to save die area. (They also share an L2 cache and its TLB.) This would bottleneck performance in cases where both threads needed access to the vector pipeline. It’s not an unusual technique – many high-end processors share hardware resources between cores or threads – but it’s definitely a space/performance tradeoff.  

Cortex-X2 will obviously be the successor to the semicustom X1 introduced last year, a kind of hybrid design that allows limited customization without the complexity and expense of a full architectural license, à la Qualcomm or Apple. What kinds of customization? “We tend not to talk about that,” says Williamson. True enough. 

Over in graphics land, Mali-G710 will become the new top of the GPU lineup, with the G510 as its midrange sibling and the G310 for budget-conscious designers. Mali is certainly popular (except in smartphones, where it’s overshadowed by PowerVR), so you might expect this new generation to sport new features like, say, ray tracing. “We do a lot of research into our customers’ needs… but we’re not announcing specific support in that area… that’s for future developments.” So… that’s a no on ray tracing, then? 

New iterations of the CoreLink on-chip interconnect and updates to security were also mentioned, but with no details for either. Secure EL2 “takes [security] to the next level” and “this will be the stuff of nightmares for hackers” were the extent of the technical disclosure. 

As usual, shipment dates are hard to pin down in the IP business. ARM suggested that all of the new IP is in licensees’ hands now, but when those chips will appear in consumer products is anybody’s guess. Actually, ARM did offer one guess: that smartphone chips based on Cortex-X2, Cortex-A710, and/or Cortex-A510 might appear around the end of this year, with the phones themselves reaching the retail channel around the end of 2022. No word on other consumer, computer, or embedded items. That’s up to the chip designers and the product manufacturers and is largely out of ARM’s hands. 

What is in ARM’s hands is its product announcement strategy, and for several years now the company has transitioned from a technology firm to a marketing company. Its official rollouts are increasingly slick, with colorful presentations and well-drilled speakers, but with vanishingly little technical meat. That’s understandable. The company doesn’t need to tease engineers with interesting new innovations. We’re not their audience anymore. Investors are. Anyone who needs to know how ARM cores work or how one differs from another can get that information under NDA. For everyone else, it’s just brightly colored graphs that point up and to the right. And the big name reveal.

Leave a Reply

featured blogs
Sep 26, 2021
https://youtu.be/Ivi2dTIcm9E Made at my garden gate (camera Carey Guo) Monday: Ten Lessons from Three Generations of Google TPUs Tuesday: At a Digital Crossroads Wednesday: Announcing Helium, Hybrid... [[ Click on the title to access the full blog on the Cadence Community si...
Sep 24, 2021
Wi-Fi, NB-IoT, Bluetooth, LoRaWAN... This webinar will help you to choose the appropriate connectivity protocol for your IoT application....
Sep 23, 2021
The GIRLS GO Engineering scholarship provides opportunities for women in tech and fosters diversity in STEM; see the winners of our 2021 engineering challenge! The post GIRLS GO Engineering! Empowers Our Next-Gen Women in Tech appeared first on From Silicon To Software....
Sep 23, 2021
The Global Environment Facility Small Grants Programme (GEF SGP), implemented by the United Nations Development Programme, is collaborating with the InnovateFPGA contest. Showcase your  skills with Intel Edge-Centric FPGAs and help develop technical solutions that reduce env...

featured video

Silicon Lifecycle Management Paradigm Shift

Sponsored by Synopsys

An end-to-end platform solution, Silicon Lifecycle Management leverages existing, mature, world-class technologies within Synopsys. This exciting new concept will revolutionize the semiconductor industry and how we manage silicon design. For the first time, designers can look inside silicon chip devices from the moment the design is created to the point at which they end their life.

Click here to learn more about Silicon Lifecycle Management

featured paper

IPU-Based Cloud Infrastructure: The Fulcrum for Digital Business

Sponsored by Intel

As Cloud Service Providers consider their investment strategies and technology plans for the future, learn how IPUs can offer a path to accelerate and financially optimize cloud services.

Click to read more

featured chalk talk


Sponsored by Mouser Electronics and Bourns

Today, your circuit protection device needs to be versatile, handling a wide range of conditions with long-life low capacitance, low leakage, and state-of-the-art energy handling density. In this episode of Chalk Talk, Amelia Dalton chats with Paul Smith from Bourns about IsoMOV - a new integrated circuit protection that brings together the most important circuit protection capabilities in one efficient package.

Click here for more information about Bourns IsoMOV™ Series Hybrid Protection Component