feature article
Subscribe Now

Achronix Goes Chipless

FPGA Cores for SoC Designers

Since 2013, Achronix has been cruising along, quietly doing a decent business with their Speedster FPGA family. Their particular value proposition resonates well for certain networking and acceleration applications, and they’ve mined a good business by strategically poking at gaps in the Xilinx and Altera product offerings in certain markets. More recently, their Accelerator-6D PCIe board – bringing FPGA-based compute acceleration to existing server installations – has gotten good reviews. 

At the same time, though, they’ve apparently also been stealthily working a novel angle – licensing their FPGA IP for teams doing complex custom SoC designs. This week, the company made a formal announcement of their new “Speedcore Embedded FPGA Technology,” which is exactly what the name implies. In fact, Achronix claims that several companies/teams are well into the design process using Achronix FPGA IP in their custom designs. Speedcore essentially strips the FPGA core logic out of a Speedster FPGA device and makes it available as a scalable IP block that can be fabricated on TSMC 16nm FinFET technology.

Unlike most commercial IP, Achronix is offering essentially a generator that creates custom-sized physical IP blocks, rather than the synthesizable RTL that most IP companies ship. For FPGA fabric, this is critical, as the layout is fundamental to the proper function of the fabric, and the FPGA routing resources must be scaled to fit the size and configuration of the particular array, including the number of LUTs, number of DSP blocks, amount of memory, etc. 

This is not the first time anyone has had the idea to serve up FPGA technology as IP. As of this writing, Flex Logix, a startup, is well down the path of offering licensable FPGA cores. But Achronix has put some good thought into the strategy, and they are the first company we know of that currently produces both FPGAs and embedded FPGA IP. The usual biggest issue with FPGA-as-IP is tools. It’s an enormous undertaking to sell and support a robust design tool suite that will allow designers to customize arbitrary FPGA fabric in an SoC of unknown configuration. In fact, it’s hard to provide FPGA tools for even a stable, known FPGA – a problem that has doomed many an FPGA startup over the years.

Achronix, however, has a stable, proven tool suite that has been cranking out designs with their fabric for years now. For some parts of the flow, they partner with Synopsys, who produces some of the most respected tools in the EDA industry. The trick in selling IP instead of chips, then, is to make the tools configurable to match particular implementations of the FPGA fabric in custom designs. For this, the Achronix core generator also builds configuration files that set up the tools to match the particular FPGA core being used. 

The alternative, of course, is to park an FPGA next to your custom chip. But having the FPGA fabric actually inside your SoC brings a host of functional, performance, and power advantages. First and foremost – the bandwidth achievable between the FPGA fabric and the rest of your design is many times larger than with a two-chip solution. Second, the latency between the FPGA part and the non-FPGA part is significantly lower. Third, the power consumption is dramatically better if data going between the FPGA and the rest of the design is on chip, since external IOs (or even SerDes transceivers) and PCB traces are involved in chip-to-chip communications. Fourth, IOs that would otherwise be used to connect the SoC to the FPGA can be freed up for other use, resulting in a smaller package. Finally, security is better since the communication between devices is not externalized.

Further, when you embed FPGA fabric in your own design, you aren’t paying for all the “extra” stuff in a typical FPGA that you don’t use. It’s a rare application that just happens to use exactly the number of IOs and SerDes transceivers on their chip, for example. This “right sizing” is bound to help with overall system cost, complexity, and performance as well. 

Achronix puts some numbers to these advantages – claiming 10x higher bandwidth, 10x lower latency (do they mean 90% lower?), 50% lower power, and 90% lower cost. If you were planning to park an FPGA next to your chip, those are some pretty compelling numbers – even if you adjust for typical semiconductor marketing spin.

The real “killer app” for embedding FPGA fabric is compute acceleration. While many have offered the idea of sticking some FPGA fabric in a design to allow post-tapeout “fixes” or to adapt to changing IO standards, few real-world examples of this “insurance” have been seen. But if your design is doing high-performance computing in an area such as embedded vision where the FPGA’s massive fine-grained parallelism and extremely low power consumption would be a win, this could be the perfect solution.

Accelerated computing with FPGAs is exploding right now, with Intel reportedly acquiring Altera largely because they want to use FPGAs in datacenter-class processor chips. If Intel is willing to spend $16B for some FPGA IP to put in their devices, Achronix Speedcores suddenly seem like a real bargain! (OK, we know there’s way more involved in the Intel scenario, but humor us a bit).

Of course, Xilinx and Intel/Altera both offer FPGA SoCs that combine FPGA fabric and IO with ARM-based processor subsystems and a few nice peripherals. If those devices meet your needs, you probably won’t be doing a custom SoC anyway. If you are, however, the Achronix Speedcore offering is probably worth a serious look.

 

11 thoughts on “Achronix Goes Chipless”

  1. Kevin,

    You need to do a little more research. Achronix CEO Holt was discussing this hail mary pass back in 2012. So it’s not some stealth mode reveal.

    http://www.eetimes.com/document.asp?doc_id=1279972

    Here is my history of Achronix.

    1. Fastest FPGA on the face of the planet. Total fail. This was the asynch FPGA concept with the pico pipes. Complete disaster and waste of time and investor money.
    2. CEO Holt finally gets fired and replaced after years of pico pipe futility.
    3. New CEO from Altera and comes out with a regular FPGA fabric to try to compete head to head with Stratix and Virtex high end devices. Complete disaster with no significant wins or sales. Nobody has ever had the ability to succeed against the XorA high end.
    4. Fall completely behind Xilinx and Altera with no new FPGA in several years. First and last Speedster FPGA is announced 4/24/12.
    5. Xilinx US+ is on TSMC 16FF and Altera S10 is on Intel 14 nm. Soon to be 10nm and 10nm or 7and7.
    6. Try desperation play to create a server accelerator card to try and generate sales.
    7. Last ditch hail mary pass to sell the FPGA fabric as an IP core. Moving to the IP provider biz.

    There is already a leader in that space though and the name of the company is Flex Logix.

    http://www.flex-logix.com/

  2. Welcome back @gobeavs! We’ve missed you.

    We didn’t know we just had to mention Achronix. What is it with you and them anyway? Did they kick your puppy or steal your bike?

  3. Pingback: switch
  4. Pingback: friv
  5. Pingback: DMPK Analysis
  6. Pingback: read

Leave a Reply

featured blogs
Oct 20, 2020
In 2020, mobile traffic has skyrocketed everywhere as our planet battles a pandemic. Samtec.com saw nearly double the mobile traffic in the first two quarters than it normally sees. While these levels have dropped off from their peaks in the spring, they have not returned to ...
Oct 20, 2020
Voltus TM IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the... [[ Click on the title to access the full blog on the Cadence Community site...
Oct 19, 2020
Have you ever wondered if there may another world hidden behind the facade of the one we know and love? If so, would you like to go there for a visit?...
Oct 16, 2020
[From the last episode: We put together many of the ideas we'€™ve been describing to show the basics of how in-memory compute works.] I'€™m going to take a sec for some commentary before we continue with the last few steps of in-memory compute. The whole point of this web...

featured video

Demo: Inuitive NU4000 SoC with ARC EV Processor Running SLAM and CNN

Sponsored by Synopsys

Autonomous vehicles, robotics, augmented and virtual reality all require simultaneous localization and mapping (SLAM) to build a map of the surroundings. Combining SLAM with a neural network engine adds intelligence, allowing the system to identify objects and make decisions. In this demo, Synopsys ARC EV processor’s vision engine (VPU) accelerates KudanSLAM algorithms by up to 40% while running object detection on its CNN engine.

Click here for more information about DesignWare ARC EV Processors for Embedded Vision

featured paper

Fundamentals of Precision ADC Noise Analysis

Sponsored by Texas Instruments

Build your knowledge of noise performance with high-resolution delta-sigma ADCs. This e-book covers types of ADC noise, how other components contribute noise to the system, and how these noise sources interact with each other.

Click here to download the whitepaper

Featured Chalk Talk

Power Supply Design

Sponsored by Mouser Electronics and KEMET

There is a bewildering range of choices for components for power supply design. Considering EMI protection, surge protection, transformers, rectifiers - the list goes on and on. In this episode of Chalk Talk, Amelia Dalton chats with Nick Stephen of KEMET to sort out the puzzle of power supply component selection, and to look at the latest trends and best practices in power supply design.

Click here for more information about KEMET Electronics METCOM MPX1 Metal Composite Power Inductors