It’s always fun to fantasize about Ferraris and FinFETs. After all, what true engineer doesn’t get a little tingly talking about terabits of bandwidth, single-digit nanometers, and gazillions of LUTs. But, in practical terms, the vast majority of us don’t have an actual application need for the biggest, fastest FPGAs and SoCs on the market. And, while it’s fun to watch and speculate about which company can cram the most transistors onto an integrated circuit, the reality is that, for most of us, our actual requirements are much more modest.
Fortunately, the programmable logic companies realize this, and, in the midst of all the marketing bravado and chest beating about the new high-end FPGA families, Xilinx is announcing a major upgrade to their non-bleeding-edge families – Zynq, Artix, and – back by popular demand – Spartan.
Yep. We thought Spartan was dead too. Welcome back little buddy!
Several years ago, when Xilinx launched the 7 series – with its consistent fabric architecture from top to bottom, they told us that the new families would be Virtex, Kintex, and Artix. Wait, what? No Spartan? We were bummed. Spartan was a perfect product for the range. But time and technology move ever forward. We concluded that Artix must be the Spartan for a new age, licked our wounds, and went on with life. Now, little Spartan is reinstated in its glorious place at the back of the train – but more on that in a bit.
All of the new devices are fabricated on the proven 28nm TSMC process node, and this actually validates what we’ve been saying about the economic slowdown of Moore’s Law. As we move ahead, fewer and fewer devices and applications will reap actual price, performance, and power benefits from the latest, smallest geometries. In particular, we think 28nm will have very long legs, as the benefits for moving to 20nm are modest compared with the typical one-node jump, and the cost and risk of doing a FinFET 16nm/14nm design are still prohibitive for chips that don’t actually need the benefits that node brings.
For Xilinx, this announcement also represents a rounding out of the current lineup, putting the whole tribe under the Vivado banner. This means that tools, IP, and the whole ecosystem really are now consistent across all of Xilinx’s families, and that means scalability and consistency for customers.
For the specifics, let’s start with the top of the heap – the Zynq 7000. Sure, we’ve all been ooooh-ing and aaaahhh-ing over the new Zynq Ultrascale+ with its quad-cores and chrome tailpipes, but, if the Zynq family is to offer a plausible range for competing with ARM-based SoCs from the likes of NXP, there needs to be a little love on the single-core end of the spectrum as well. So, the company is rolling out new Zynq-7000 single core devices at a lower price point than the existing Zynq offerings. The entire Zynq range – from these single-core devices to the new UltraScale+ MPSoCs – are supported by the same design tool flow and offer the same multi-layered safety and security features, which are critical for the type of IoT applications that are the sweet spot for this technology.
The Zynq-7000 family now includes members with single- or dual-core processors, LUT counts ranging from 28K-85K LUTs, 1066 Mbps DDR3 interfaces, and 6.25 Gpbs SerDes. If you’re thinking of pairing a conventional ARM SoC with an FPGA, Zynq is probably a much more attractive option – better integrated, supported top-to-bottom with one tool flow, sporting better-engineered connectivity between the FPGA and SoC sections of the design, and most likely manifesting much better overall performance and power efficiency. We can’t say whether the total BOM will be lower or not, but it’s likely – particularly considering the extra PCB real estate that a two-chip solution would require.
Since SoC FPGAs like Zynq are far more likely to go head-to-head fighting for sockets with conventional SoCs (often SoCs plus a smaller FPGA), it is critical for Xilinx to have a whole range of devices from which to choose. Without this new single-core option, the company wouldn’t even be in the competition for the large number of mainstream applications that can get by with a single ARM core. Providing a more complete range actually makes the Zynq option more viable from top to bottom, given the ramp-up requirement for engineering teams embracing FPGA-enhanced SoCs for the first time.
Moving down the line, the Artix cost-optimized transceiver-having family has taken on new members. Artix-7 now reaches from 12K-200K LUTs, with 1066 Mbps DDR3 interfaces and 6.6 Gbps SerDes transceivers. For those who need transceivers but want the smaller, more economical cost-optimized devices, the Artix-7 family now provides a more attractive alternative.
Finally, yep, our little buddy Spartan is back – with the new Spartan-7 series. Spartan-7 is basically Artix-7 without the SerDes (OK, Spartan 7 does have one smaller device and doesn’t have the largest LUT count that Artix-7 supports.) Spartan-7 is also fabbed on TSMC 28nm, and it ranges from 6K-201K LUTs. The big news here, though, is Vivado support. Now, with Spartan-7, Spartan lovers don’t have to go back to the old ISE tool flow. Vivado can take you from the top of the UltraScale+ range down to the bottom of the Spartan-7 range. The takeover is complete.
While these devices round out Xilinx’s overall offering nicely, probably the more important thing is the now-consistent set of tools, IP, and ecosystem that applies to the entire Xilinx range. Plus, with the re-birth of Spartan, we now have a viable low-cost product for applications that don’t need SerDes transceivers. That opens up a whole universe of interesting applications in the maker and innovative startup arena.
In the big competition with the newly formed Intel/Altera, this announcement looks like a bolstering of fortifications. Xilinx is in an excellent position with a solid lineup of silicon, a robust tool flow, a solid market share lead, and a great infrastructure supporting their customers. With the combined resources of Intel and Altera amassing forces and taking aim, it is a good thing for Xilinx to be well prepared.
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