feature article
Subscribe Now

Patents Expired! Create Your Own Processor!

Make a 32-bit SuperH CPU in Your Spare Time

“Why, it’s turtles all the way down!” – anonymous, in describing recursive philosophy

Now that we’re well into the 21st Century, some of the microprocessors we used in our salad days have fallen into the public domain. Case in point: Hitachi’s SuperH CPU.

If you’re not a Japanese developer, you may not remember the SuperH (or Hitachi, for that matter). Remember the Sega Saturn or Dreamcast video games? They both used SuperH processors. In fact, later generations of SuperH were tweaked specifically to accelerate Sega’s graphics. SuperH was also among the first RISC processors to use a “compressed” instruction set (i.e., a 32-bit processor with 16-bit instruction words). It was the precursor to ARM’s Thumb, MIPS-16, and other compressed ISAs. For a while there, SuperH was one of the most popular 32-bit RISC chips on the planet. Then progress happened.

But that’s all good news for you, because SuperH just passed its 25th birthday! And as a wholly unintentional birthday present, most of its patents have now expired. That means it’s now legally tenable to clone the entire 32-bit SuperH architecture from scratch and make your own microprocessors – for free.

In fact, it’s easier than that. You don’t even have to build your own SuperH because it’s already been done for you. The bit stream is yours for the asking, along with the coding tools and even a working Linux port. For the price of a $50 FPGA board, you could have a working Linux system by this afternoon. Ain’t (vintage) technology grand?

The project is called J-Core and it’s available here. Why “J-Core” and not “SuperH?” Because trademarks are not patents, and Hitachi’s trademark on the name SuperH hasn’t yet expired. (Presumably, the developers of J-Core would be able to rename it SuperH at some point in the future, if they so choose.)

The point of creating J-Core was to establish an entirely open-source hardware/software platform – one where the developer could examine and verify (and potentially modify) absolutely everything, from the internal CPU architecture, to the compiler, to the operating system’s kernel or device drivers. There’s a certain quasi-political interest in that concept from many developers; to everyone else, it’s just a free microprocessor with a free tool chain.

As modern processors go, J-Core isn’t quite all there. There’s no MMU, for example, nor any support for floating-point arithmetic, threads, or multicore implementations. Housed in a Spartan 6 FPGA, it’s not very fast, either. But it is free and it boots Linux out of the box. The MMU and FPU support will come later, as the last few SuperH patents expire.

You might argue that running Linux on a non-MMU processor is an exercise in futility. As one user commented, “…it really makes you appreciate what you get with an MMU.” So as it stands, the J-Core/Linux combination is probably better suited to single-purpose embedded devices, as opposed to miniature multitasking systems. But that’s up to you.

Temporary limitations aside, J-Core/SuperH is a very capable 32-bit RISC processor, even if it is getting on in years. Its performance per clock cycle is equivalent to any RISC chip’s, while its code density is quite a bit better.

The former is because all RISC architectures deliver more or less the same performance. That’s by design. The credit for the latter feature goes to the architecture’s 16-bit word length, an unusual – almost heretical – feature when SuperH was first created. RISC processors, by definition, always used fixed-length instruction words that matched their native data word. Thus, 32-bit processors used 32-bit data and instructions; 64-bit CPUs used only 64-bit words, and so on. But because SuperH was always intended to be used in embedded systems and cost-sensitive consumer devices (most famously Sega’s game consoles), it was designed to minimize memory usage. Hence, the 16-bit instruction word.

The heresy paid off. A pair of researchers working out of Cornell and Sweden’s Chalmers Technical University pegged SuperH’s code density as the best of any RISC architecture they tested, and almost on par with x86, the gold standard for tight assembly code.

The only hitch is that it requires some tricky hardware to “un-compress” those 16-bit instructions into what the SuperH execution unit actually wants. There is no free lunch. But, unless you’re allergic to gates and multiplexers, it’s a good tradeoff to make.

So… interesting toy or real-life processor resource? J-Core can be either. It’s certainly easy enough to get started, and you can follow the progress of future generations of the processor here. (Basically, as the remaining patents expire, their salient features will appear in subsequent J-Core generations.) The FPGA implementation comes with a complete walkthrough for first-timers.

But if you ever get serious about using J-Core in an actual production-level product, its VHDL description can be retargeted for ASICs instead of FPGAs. J-Core is intended to be used for reals, not just as a teaching toy. 

There are plenty of processor architectures in the world. There are even free 32-bit RISC architectures in the wild (OpenRISC, LEON, RISC-V, et al). But most of those are “synthetic” processors designed either as teaching aids or as belligerently open-sourced projects, not as production processors designed for commercial use. SuperH – sorry, J-Core – is among the first “real” processors to be reverse-engineered as a free replacement for the once-commercial product. As such, it comes with an established tool chain, a proven track record, and 20+ years of production history. You can’t ask much more of a free processor.

 

One thought on “Patents Expired! Create Your Own Processor!”

Leave a Reply

featured blogs
Oct 25, 2020
https://youtu.be/_xItRYHmGPw Made on my balcony (camera Carey Guo) Monday: The Start of the Arm Era Tuesday: The Gen Arm 2Z Ambassadors Wednesday: CadenceLIVE India: Best Paper Awards Thursday:... [[ Click on the title to access the full blog on the Cadence Community site. ]...
Oct 23, 2020
Processing a component onto a PCB used to be fairly straightforward. Through-hole products, or a single or double row surface mount with a larger centerline rarely offer unique challenges obtaining a proper solder joint. However, as electronics continue to get smaller and con...
Oct 23, 2020
[From the last episode: We noted that some inventions, like in-memory compute, aren'€™t intuitive, being driven instead by the math.] We have one more addition to add to our in-memory compute system. Remember that, when we use a regular memory, what goes in is an address '...
Oct 23, 2020
Any suggestions for a 4x4 keypad in which the keys aren'€™t wobbly and you don'€™t have to strike a key dead center for it to make contact?...

featured video

Better PPA with Innovus Mixed Placer Technology – Gigaplace XL

Sponsored by Cadence Design Systems

With the increase of on-chip storage elements, it has become extremely time consuming to come up with an optimized floorplan with manual methods. Innovus Implementation’s advanced multi-objective placement technology, GigaPlace XL, provides automation to optimize at scale, concurrent placement of macros, and standard cells for multiple objectives like timing, wirelength, congestion, and power. This technology provides an innovative way to address design productivity along with design quality improvements reducing weeks of manual floorplan time down to a few hours.

Click here for more information about Innovus Implementation System

featured paper

Designing highly efficient, powerful and fast EV charging stations

Sponsored by Texas Instruments

Scaling the necessary power for fast EV charging stations can be challenging. One solution is to use modular power converters stacked in parallel. Learn more in our technical article.

Click here to download the technical article

Featured Chalk Talk

ROHM BD71847AMWV PMIC for the NXP i.MM 8M Mini

Sponsored by Mouser Electronics and ROHM Semiconductor

Designing-in a power supply for today’s remarkable applications processors can be a hurdle for many embedded design teams. Creating a solutions that’s small, efficient, and inexpensive demands considerable engineering time and expertise. In this episode of Chalk Talk, Amelia Dalton chats with Kristopher Bahar of ROHM about some new power management ICs that are small, efficient, and inexpensive.

Click here for more information about ROHM Semiconductor BD71847AMWV Programmable Power Management IC