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EDA: Expanding or Fading?

The Nature of a Bursty Business

Those of you who have been with us a long time may well remember that our humble journal didn’t start out as EE Journal. In fact, it started as FPGA Journal, with founder Kevin Morris as chief editor, writer, cook, and bottle washer. A few years later, we added a new Embedded Technology Journal (whose current embodiment is ably managed by Jim Turley). Only several years after that did we take on IC design specifically, which is when yours truly joined the fray.

And then we opened our umbrella wider, covered more topics, and consolidated into a single EE Journal, with a number of specialized “channels” that would allow our readers to on their specific areas of interest. Out of the IC newsletter were born two channels: EDA (for the tools) and Semiconductor (for the underlying silicon technology).

This piece is about EDA – and yet, as I look around at our other broad-based competitors, I’ve come to realize that we appear to be the only ones in that class who still call out a separate focus area for EDA. The other sites I checked may cover EDA topics in various contexts, but they no longer appear to track that industry directly.

Does that mean that EDA is losing relevance? I’ve historically had a few year-end reviews where I commented on how EDA might have been quiet for that particular year. And the EDA industry is certainly cyclic, with rashes of start-ups getting going with new tools that are interesting to talk about, ending with various Big Guys buying them out. (For the most part.) But cyclic industries are certainly worth watching for when the cycle comes ‘round again. So why have others demoted the space?

I certainly won’t speculate on the motives of our compatriots in this business, but here’s what strikes me as curious: EDA focus seems to be fading even as EDA is becoming more important.*

Let’s first try to put our arms around what qualifies as EDA. Historically, the things that EDA covered were really far short of all designs of things electronic. There were, realistically, three subsegments of EDA: IC design tools, FPGA design tools, and PCB design tools.

From our standpoint, Kevin covers FPGA tools. Realistically, there isn’t a robust secondary market for FPGA tools (other than the occasional utility or high-abstraction front end). In the end, the FPGA companies themselves control their tool destinies, and the prices they have historically charged (not very much) have made the space uninteresting to companies that would have to survive without silicon revenue to subsidize the software.

PCB tools typically address a very different audience from both FPGA and IC design tools (and, in fact, we have a separate Board channel for that).

So that leaves our primary EDA focus on silicon design tools. But, as we’ve seen before, EDA’s role is expanding. It has taken on embedded design through the evolution of the system on chip (SoC) – including software, and it’s grown to embrace MEMS design as mechanical and electronic meet on a single piece of silicon. The more we integrate onto a die, the more work EDA tools have to do – whether they do the work themselves or connect up to other tools that used to live in a separate, parallel universe.

So does this mean that all new interesting EDA things have pretty much been done? That EDA can slip into the background much the way the Internet, which used to be this cool new thing, is simply normal and goes without saying? Are there other big things coming?

While I don’t know specifically what our EDA friends have up their sleeves, we can engage in some informed speculation. The big EDA changes tend to come from two directions: expansion of scope (like embedded and MEMS) and introduction of new silicon problems to solve. You might think of these as coming from above (system integration) and below (silicon technology).

Surprisingly, the first of those two seems to attract the least attention – perhaps because it’s something that happens more gradually, even insidiously. Looking ahead at one example, silicon photonics will start rearing its head more often as something to be integrated with other circuits.

The bottom-up angle, on the other hand, has attracted the most focus. We’ve seen the changes that FinFET technology required. That’s more or less done (at least, the shock-to-the-system part), and it has quieted down a bit. As new transistor configurations arise – and they will arise – we’ll see more new problems that EDA tools will have to solve.

EUV’s ongoing delay has forced EDA to invest heavily in multiple patterning – a huge topic that wouldn’t have been needed at all if there were an ongoing lithography path enabling finer and finer features. But there isn’t; even with EUV, we have only one new jump in resolution. What about after that? Yeah, multi-EUV patterning may be a thing.

Then there are new materials and meta-materials, each having a particular purpose that can’t be accommodated with traditional materials. So those material properties will need to be understood by EDA tools at some level. Yes, your average chip designer may not delve that deep, but that makes the tools that much more important – so that they can abstract away such low-level considerations from everyday chip design.

Completely independently of this new technology cycle is the complete-tool-rewrite cycle, where keepers of an older tool finally cry, “Uncle!” and start over for better performance, capacity, and/or accuracy.

So, with all this potential new stuff coming, why these giant quiet periods? Well, the cycle seems to go something like this:

  • Silicon folks debate new structures and approaches.
  • They then narrow down the most likely ones for development, and they need “pathfinding” tools for that. The EDA Big Three typically get involved at very early stages with proof-of-concept tools to get the technology to a state where it can be commercialized. That can take some years.
  • Then we might get an announcement – this is the cool moment when we get to find out what new tricks have been employed to batter old problems into submission. And they tend to come in waves. When one company’s tools are featured in a foundry’s new reference flow, you know that the others aren’t far behind.
  • And even after that, we wait until system requirements demand the new technologies and until improvements reduce the costs of those technologies so that designers will start using them on a regular basis. And that can be more years.

So we get these bursts of big change buffered by periods of waiting.

It can be tough to wait around for stuff to happen. But the payoff is that, when stuff does happen, it can be both important and interesting. So we’re content to keep our eyes on EDA and be patient.

EDA: your move.

 

*Most people measure the “size” of industries using market numbers. I’m not: I’m using a looser definition, characterized by how much new technology is making the news. So none of this discussion has to do with revenues going up and down; this is about new stuff that would be interesting to an engineer.

 

2 thoughts on “EDA: Expanding or Fading?”

  1. Most of the current EDA tools and methodology are well past their prime. The high variability in sub 45nm Silicon means you want to move to asynchronous design techniques, and the move to die-stacking means you need aggressive power management – being able to switch quickly from full power to subthreshold power levels.

    FDSOI looks like a better technology for doing some of that, but the current digital design flow can’t handle body-biasing properly.

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