The SmartFusion®2 system-on-chip (SoC) FPGA is differentiated from other FPGAs by its low power capabilities that enable orders of magnitude lower power operation for low duty cycle applications. The device family includes important low power features:
• Industry’s lowest static power
• Flash*Freeze real-time low power state
• ARM® Cortex™-M3 low power modes
• SoC peripheral low power modes
In systems that operate reactively or periodically, SmartFusion2 FPGAs can dramatically reduce power. Reactive operation is defined as being in a standby state waiting for some activity or event before initiating processing. The reactive system returns to the standby state after processing is complete. Following are examples of reactive systems:
• Patient health monitor alarm that is activated when a patient falls down
• Remote sensor initiating communication based on event detection
Periodic operation is defined as consisting of some activity that must be performed on a recurring basis. These systems performs some processing and then enter standby mode. At a fixed time interval, the system repeats the processing function and returns to standby mode. Following are examples of periodic systems:
• Many standard wireless protocols
• Patient heart rate monitor or similar that measures the pulse pressure periodically
• Remote sensor periodically measuring information
Saving energy in periodic and reactive systems is achieved by moving into a very low power state when processing is not necessary. This is possible within SmartFusion2 FPGAs using the ARM Cortex-M3 low power modes and Flash*Freeze mode in the FPGA fabric and I/Os. The capabilities of Flash*Freeze mode, however, are completely unique in FPGAs. Flash*Freeze technology enables the rapid stopping and starting of the FPGA fabric and related I/Os while preserving the state of the FPGA fabric and dramatically reducing power. The time to enter Flash*Freeze mode is approximately 100 ?s; the time to exit Flash*Freeze mode is also approximately 100 ?s. While in Flash*Freeze mode, the state of the FPGA is maintained so that upon exit, the device continues to operate where it left off.
