Board design and layout used to be so simple. All you had to do was make sure that all the metal parts that were supposed to touch did, and all the metal parts that were not supposed to touch didn’t. Handy software tools did all the heavy lifting, and there were about a zillion different possible layout solutions – all of which worked.
That was back in the day – before all this high-speed serial nonsense. Now, thanks to our multi-gigabit lifestyle, just making the metal touch doesn’t cut it anymore. We have to worry about signal integrity (SI). All those zeroes and ones flying through PCB traces start to cut corners, and our eyes slowly begin to close…
At first, it was just the radical, wind-in-their-hair, super-high-speed, extreme designers that had to worry about this stuff. With the electronic design equivalent of wingsuits, they daredevil-dived their way into the billions of bits per second – taunting the gods of analog effects (and keeping the BERT scope people in business.) Over time, though, their ways became commonplace. Standards like PCI Express and DDR3 brought signal integrity problems to the masses, and all of us had to go back to school for wingsuit training. No matter how determinedly we avoided analog in school, it was coming back to haunt us in our most sacred of digital hideouts.
Cadence feels our pain. Last year, they acquired Sigrity – one of the leading providers of stand-alone signal integrity solutions. Sigrity has a robust set of tools for signal integrity analysis that have been in wide use for years. Now Cadence has integrated some of the most important Sigrity capabilities into the popular Allegro PCB solution, and that integration brings us the ability to gain back some of the sanity of the old days with our modern PCB design. In fact, they didn’t stop with just PCBs. Signal integrity is a major issue with IC packaging and with the latest stacked-silicon, system-in-package (SiP) designs.
Cadence offers three flavors of Allegro aimed at those three problem domains – PCB, ICP (Packaging), and SiP (stacked-silicon). Now they have announced Allegro Sigrity SI – to work with all three of those. The new signal integrity features are integrated into the constraint-driven flow for board and package design. Capabilities include layout floorplanning and editing, schematic-level topology exploration and top-down signal integrity simulation, construing development and capture, signal integrity analysis model library management, and SI-related error rule checkers.
On top of the base “Allegro Sigrity SI” features, there are options for power-aware SI, serial link analysis, and package assessment. The first option, PowerSI, provides efficient PCB interconnect extraction and integrates with the IC and Package versions as well. Cadence’s model connection protocol (MCP) connects signal, power, and ground across fabrics. Rather than doing signal integrity simulation with idealized power (which gives us a rosier-than-real picture of our SI situation), power-aware analysis combines reelections, crosstalk, and simultaneous switching effects on power in the SI picture. This results in a much more accurate assessment of the real-world performance of our design.
The second option, “Serial Link SI,” provides an environment for simulating and assessing high-speed serial links, such as multi-gigabit SerDes, in order to enable design of high-integrity IC package and PCB implementations. Serial Link SI includes a compliance workflow that simplifies the process of validating compliance with industry standards for plug-and-play SerDes links.
The final option, Package Assessment, is aimed at IC package design, analysis, and model extraction. SIgrity XtractIM integration allows edits to be made in the base SI tool and then quickly investigated with fast RLC extraction and assessment. The resulting models are suitable for use in high-speed applications where packaging performance is a critical issue. The tool supports single-die, multi-die, and SiP designs as well as both wire-bond and flip-chip attachment technologies, and it can extract models of entire packages or of select performance-critical nets.
Cadence is also working on integration of the Sigrity Power Integrity tool suite with Allegro. As we discussed last year, Cadence has an existing power integrity capability (Allegro PI). Cadence plans to offer a no-cost upgrade for current Allegro Power Integrity customers to the new integrated solution when it’s available. Until then, the Sigrity Power Integrity tools continue to be offered as a stand-alone suite. Cadence says they plan to continue offering the other Sigrity solutions as stand-alone suites as well, so don’t get all worried that they’re taking away your Mentor or Zuken flow. You’re still good. Often, EDA companies use these acquisitions to try to force customers’ hands into switching boats when all they really wanted was a new oar. It’s good to see Cadence playing nice in the best interests of their customers.
Integrity doesn’t come cheap, so don’t be expecting the new Sigrity-based solutions to be at the low end of the PCB food chain. Cadence says that pricing will be in line with what one would expect in an enterprise-level board design solution like Allegro. The new Allegro integration features are just the most recent in a series of steps the company has taken since acquiring Sigrity. The first, last July, was a “look-and-feel” overhaul to make the tools feel like the Cadence brand. Next came single-user license suites in November, and now we have integration of major components with Allegro. Next, we expect to see the company integrating the Power Analysis capabilities with Allegro as well.
Board and package design is an interesting segment of the EDA market. For years, EDA companies considered PCB a “cash cow” – content to quietly roll in big revenues while reinvesting very little in advancing the technology. In recent years, however, changes in the big technology picture, including high-speed serial links, advanced packaging techniques, and ultra-high density design have created new opportunities for differentiation in this critical space. As a result, we’re seeing companies like Cadence put a new emphasis on creating value that applies to a much wider swath of designers than the big EDA companies’ traditional IC-biased strategies. For most of us, this is a welcome change.