Remember when you were a kid, playing with Legos? You could build tons of things with it – maybe. It depended on the size of your kit. Because the bigger kits had more variety.

If you had only the standard-issue rectangular pieces, you could build lots of walls and such that went straight up, and perhaps some pyramidy things – up to a point. Actually, that was the one thing you couldn’t build them up to: a point. But, well, everything had a rather right rectangular look.

If you really wanted to increase your options, you needed additional square pieces and the wee ones, and then perhaps some specialized rounded bits for corners and cornices and festive filigree. (Of course, then they got all carried away and created kits that were pretty much good for only one thing, but we won’t worry about that).

The point being, it’s great to invent the one rectangular piece and show what you can do with it, but you’re hitting your stride when you can fill out the selection in order to enable a wider range of edifice.

Intel demonstrated this step at IEDM last month. Having proven a FinFET for their processors, they took the next step to enable things that aren’t processors. And having to do this is a relatively new requirement.

There was a time when you built logic on a logic process and analog on an analog process and memory on a memory process and power stuff on a high-voltage process. Problem is, now everyone wants to mix and match all of this stuff on a single monolithic SoC. So the prior logic Lego now must be supplemented with other Lego shapes to enable all of the stuff that will need to be squeezed together on a single piece of silicon.

We’ve sort of been dealing with this for a while, the difference now being that, at 22nm, Intel moved from planar transistors to FinFETs – but only the standard rectangular ones (metaphorically speaking – yes, the fins are still more triangularish than rectangular in cross section). So this year they filled out the rest of the kit with the remaining bits and bobs necessary to create a full SoC. The kit includes a collection of six different FinFET options in three families:

–        High-speed logic

• High performance (HP)
• Standard performance (SP)

–        Low-power logic

• Low power (LP)
• Ultra-low power (ULP)

–        High-voltage

• 1.8 V
• 3.3 V

The differences between these guys are mostly straightforward, although some of what’s going on is a tad vague. The high-speed devices both have 90nm gate pitch; it’s the gate length that changes: 30nm for HP, 34nm for SP.

When moving to the low-power devices, it’s less clear specifically what changes. They spend some time talking about how great the FinFET architecture is for low power, but that’s not helpful – they’re also using that architecture for the high-speed stuff. I suspect one of the big clues is the note of using a fully-depleted fin (given suggestions that, in some cases, fins are being doped… maybe this is well known and I missed the memo…). They also make reference to junction engineering to minimize leakage.

The upshot is that, for the same 90-nm gate pitch/34-nm gate length, the I_dsat goes from 0.71 to 0.41 mA/µm and the I_off goes from 0.59 to 0.37 mA/µm. Move the gate pitch out farther to 108nm, with a 40nm gate length, and you get the ultra-low-power device (with I_dsat of 0.35 mA/µm and I_off of 0.33 mA/µm). They say that the performance they get from these low-power devices is a 50% increase over 32nm planar devices and is a record to date for these operating conditions.

Then we move into high-voltage territory. OK, to be fair, this is high voltage for legacy interoperation, not for driving the transformer on that pole outside your office. The 1.8-V device can be used for 1.5-, 1.8-, and 3.3-V operation; the 3.3-V device is for 3.3- and >5-V operation (they don’t specify an upper limit… While we’re assuming this isn’t for 500-V devices… it might be fun to try… once… moreso if it’s on someone else’s budget…).

They use a different gate oxide for these guys – a “composite high-? oxide,” and a look at their cross-section photos makes it clear that the dielectric is thicker than that of their logic siblings. The geometry changes as well: gate pitch is at least 180nm for 1.8-V devices and 450nm for 3.3-V devices. The gate length pushes out to 80nm and 280nm, respectively. They say that they also achieved 50% better drive current on these as compared to 32nm devices.

As to interconnect, they claim to offer 8-11 layers using low-? and ultra-low-? carbon-doped oxide dielectric, but in their diagram they show 2-6 1x pitch layers, a 1.4x pitch layer, 2 2x layers, 2 3x layers, and 1 4x top layer. Using my arithmetic, that gives up to 12… Metal 1 is different in that it requires double-patterning; none of the other layers does. The top layer is also different in that, in addition to routing global power and ground, it’s used for spiral inductors – it’s significantly thicker than the others.

They also have added a MIMCAP: this appears to be a capacitor built, not out of diffusion, but using two adjacent metal layers – metal-insulator-metal (MIM). This affords a capacitor that they say can be packed in higher density. Yes, they have regular diffusion and finger capacitors as well and claim that their precision resistor variation is less than 15%. For the analog jockeys.

Finally, they have a selection of SRAM cells, including a high-density/low-leakage (HDC) cell, a low-power (LVC) cell, and a high-performance cell for single-port memory. They also have synchronous and asynchronous dual-port cells.

And that pretty much fills out the Lego set. Off the top of my head, only DRAM cells are missing – and I don’t hear a lot of folks wishing they could include them in their SoCs. Just like you’re not going to find GaN or SiC power transistors on there.

Of course, Intel has gone to FinFET long before anyone else, so it’s not like many of you will be designing using these specific devices. Unless you’re designing for Intel. For everyone else – well, it’s about as useful for building SoCs as Legos are.