Modern SOC realization requires a development effort beyond that of traditional hardware verification. Creating a complete application-ready SOC platform now includes pre-tapeout software validation and hardware/software co-verification using full-chip RTL models. These billion-cycle scenarios are often beyond the scope of HDL simulation, but are ideal for emulation using EVE’s ZeBu hardware-assisted verification platforms.
 Altera® FPGAs and SoCs with FPGA AI Suite and OpenVINO™ Toolkit Drive Embedded/Edge AI/Machine Learning ApplicationsSponsored by Intel Describes the emerging use cases of FPGA-based AI inference in edge and custom AI applications, and software and hardware solutions for edge FPGA AI. |
