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Does the Hype Get in the Way of the Message?

I know most of you reading this are engineers and consequently never allow emotion to get in the way of logical decision making. So it would be unlikely that you would not take something seriously, just because the razzmatazz surrounding it was overstated: you wouldn’t react, either positively or negatively to marketing hype, would you?  You would just evaluate the product on its technical merits, wouldn’t you?

All too often the marketing and PR teams try desperately to make extravagant claims to hide the essential ho-hum nature of the announcement. I have been there, and, every day, as I read the new product announcement press releases, the people writing them have my sympathy – at least some of the time. We know that technology progresses. The 10 Meg go-faster do-hickey will hold the speed crown for only a short period of time, so it is understandable that the press release will be positive about the leadership. Sometimes you feel that the team is groping for a feature:  “The fastest do-hickey in a red package, released on a Thursday when there is an R in the month” is an exaggeration of the claims that are made – but some press releases do get pretty close.

Sometimes the claims are clearly overstated or misleading. A recent release appeared to be announcing 100 new components in several families. Only a very close reading showed the true message: the announcing company was demonstrating how the products from a recent acquisition filled a gap in its product range.

And sometimes the hype gets so extreme that the underlying announcement is in severe danger of being lost. This is the case, I sometimes fear, with EDA360 – the Cadence EDA initiative. If you subscribe to Fish Fry (and you should), you will have heard Amelia discussing, with an appropriate amount of cynicism, the ESC event to announce the next stage of EDA360. It is easy to mock this announcement and the entire initiative. Even some of the flummery around the announcement let it down. It was certainly not the first announcement on a trade show booth – I have attended many over the years and even organised one. It wasn’t necessary to use microphones in the confined space, as the feed-back demonstrated. Spending most of the 30-minute slot reviewing the initiative before reaching the announcement, so that the speaker from ARM had only a few seconds, wasn’t quite the right balance. All of these just got in the way of what Cadence was trying to say. And EDA360 itself is often dismissed as “a marketing ploy” or “repackaging existing things.”

EDA360 is perhaps, in part, some of those things, but it is also probably the last chance the EDA business has of getting things right. For some years now, it has been clear that the current business model is broken. The three major companies could be compared to three bald men quarrelling over a hair brush – except they aren’t yet completely bald. They are not making great profits (which is why Carl Icahn is putting pressure on Mentor Graphics), yet they are charging their customers huge sums in up-front fees and annual payments. Cadence, in a previous life, was playing accounting games to the point where it had to restate its financial figures and take a hammering on its share price. Technically, the big boys haven’t made many breakthroughs in the last few years, relying on acquiring start-up companies who have created point tools. And when you look at the companies, the point tools have often not been well incorporated into the tool flow or have even, after a couple of years, withered up and died.

At the same time, what the EDA companies are trying to do has become more and more complex. SoCs and ASICs now are very large and complex, with many millions into billions of transistors. Although they depend heavily on IP, since designing everything from scratch would be hopelessly time-consuming and inefficient, there are still significant issues with identifying, selecting, qualifying, and integrating IP, other than major elements like processor cores. And despite the smoke and mirrors surrounding ESL (Electronic Systems Level), we still have some way to go to see many chip designs starting at high levels of abstraction. At the other end of the design flow, the requirements of 22 nm geometries make an increasing number of steps in the design chain dependent on the specific process technologies. While the companies have what they label as “integrated design flows,” users frequently reach for third party tools to supplement or replace elements in the chain. Alongside laying out transistors, most SoC and ASICs require large quantities of software to be developed and verified before they can be shipped to the customers. Depending on whom you talk to, the software effort is, at the very least, of the same order of magnitude of effort and cost as the hardware development, but developing the software is undertaken in a totally separate silo from developing the hardware. And all of this has to be carried out to increasingly tight timetables, with increasingly tight budgets.

Faced with all of these issues, what have the EDA companies done? Well, while they haven’t quite adopted the ostrich position, it has been, until a year ago, very much business as usual. And then, a year ago, Cadence announced EDA360. An old journalist friend used to evaluate announcements on a Marketing BS Index, running zero to ten. At first sight, EDA360 is turning the BS dial up to eleven, but if you strip away the marketing hype, the new set of vocabulary, the new graphics, and a whole area of hand-waving, there is a solid core. Cadence has identified real problems and is working towards solving them.

One starting point in the argument is that the silicon is only a part of the problem: the chip is being designed to go into the bigger systems, which will then be sold to users. Integration starts on the chip but goes beyond it. If the EDA company is to prosper, it has to provide the tools that support the wider integration. This where we hit Cadence jargon. What EDA companies have done up until now is to support Silicon Realisation, getting transistors out of the door of the fab, and even here they have had problems. But now they should be looking at supporting SoC Realisation, not providing just silicon but also the software drivers for the specialized hardware features: a TCP/IP stack for Ethernet connectivity, for example. Finally the EDA company needs to look at System Realisation, creating a hardware/software platform so that the users can quickly begin application development. Having created a theoretical framework, which was announced a year ago, Cadence has been busy mapping real products onto it. In the year since the launch of EDA360, there have been several announcements of new products and new deals, all of which map into the overall strategy. Other companies, notably Atrenta, have come out strongly in support of the initiative.

The latest announcement, at ESC, was the Cadence System Development Suite. This includes two existing Platforms (poor platform — it means anything anyone wants it to mean), the (big breath) Cadence Palladium XP Verification Computing Platform, a big computing box that combines simulation, acceleration and emulation, and the Cadence Incisive Verification Platform. It also adds two new platforms; the Cadence Rapid Prototyping Platform, consisting of FPGA boards (with up to six Altera Stratix-4 devices) and supporting software for prototyping; and the Cadence Virtual System Platform, which uses Virtual Platforms, models of processor cores that run real operating systems and real application codes at high speeds (hundreds of millions of instructions per second) and are instruction accurate. The models are contributed by Imperas, which has optimised the OVP, open source models for Cadence interoperability.

All of these platforms are aimed at getting the software development going early, in parallel and coordinated with the hardware development. Once again, none of this is new, but assembling the package like this is new. Since the software development environment comes in a package from an EDA company, it is possible that companies may actually invest in giving the software team some of the tools they need in order to get the other half of the equation underway.

As I said earlier, I have reached a positive view of EDA360 despite the marketing hype, rather than because of it. The marketing hype is clearly driven from the top, since the spokesman/evangelist/revivalist preacher for all these events, John Bruggeman, has the resounding titles of Senior Vice-President and Chief Marketing Officer. Interestingly, the CEO of Cadence, Lip-Bu Tan, seems publicly to be taking a lower profile in this area. If EDA360 were their initiative, I suspect that Aart de Geus of Synopsys and Wally Rhines of Mentor would be leading the charge.

If it does prove to be flop, if EDA360 is no more than the smoke and mirrors that I have heard people describe it as, then Cadence and the rest of the EDA industry are going to be in even deeper trouble than they are now. The spectre of the big EDA companies being squeezed to death between the IP companies and the foundries will become even more real. If, as I hope, it is a success, companies developing SoCs and ASICS and other silicon are going to have a better opportunity of getting their products out the door on schedule, on budget, and ready to be deployed by their customers. We can only hope.

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