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Upstairs Downstairs

Navigating Amsterdam’s picturesque waterways can be a chill way to see the town (weather permitting… sometimes the chill can be a bit too literal). Many of the buildings running alongside date far back (or are made to look like they do), with features not likely to be found in a modern suburban home.

One that sticks out in particular (literally) is a beam that juts out from the peak of the roof. It extends several feet beyond the roofline, towards the street, and it has a pulley towards the end. It almost looks ornamental, but, in fact, it has a supremely mundane function: this is how you get furniture upstairs.

For the bottom floor, you can squeeze the chairs and tables through the front door and maneuver them to where they’re needed. But there’s no way you’ll get any of that up the old, narrow, steep stairways. You’re lucky to get yourself up those stairs.

So a different access mechanism is used to get things onto the upper floors. You hoist them outside and then push them through an upper window.

3D ICs actually have a similar problem: only the bottom die has access to the outside world. That’s intentional: the other dice communicate only with each other; their internal machinations aren’t relevant to outside observers, and, like so many things that might happen on the upper floors, they can occur safely beyond the reach of prying eyes.

But if you really want to be sure that what’s going on in those hidden dice is legit, you need a way to peek in there.

This thinking, to some extent, reflects a historical view, where three separately-designed dice are brought together in a single package. The combination might not have been conceived when the dice were designed, and so you’re left scratching your head once you’ve put the whole thing together: how the heck am I going to test that?

The first important development here is a change of thinking: dice that are going to be roommates should ideally be designed with cohabitation in mind. The package will contain a system that just happens to be composed of different dice. This raises challenges at two levels: the dice have to work individually and as a team.

The problem is, dice are typically tested individually when they’re still on the wafer, and they can’t be tested as thoroughly at wafer sort. Probes have never lent themselves to speed testing, and it’s even worse now since not all power and ground pads are connected on the probe card. Other pads may also remain unconnected, limiting access.

With a typical single-die product, the goal is to throw bad dice away as early as possible (to avoid the cost of further processing a die destined for the garbage), but it’s accepted that the imperfect wafer sort situation will result in additional nominal loss at final test, after packaging.

But the economics change dramatically with 3D ICs.  If two good dice are stacked with one bad die, the whole unit – including the two good dice – has to be thrown away. This bad-apple effect dramatically changes the yield equation.

This increases the need for thorough internal testing mechanisms like built-in self test (BIST). By testing as much as possible at wafer sort, the number of bad apples can be better controlled. Even tests relying on sturdy power can be handled by judiciously waiting a beat after bursts of activity to allow the power to recover from droopage before sampling the result.

This is the realm of design-for-test (DFT) technology. You build circuitry on your die that allows a minimal set of input signals to be expanded internally, managing and multiplexing the tests of numerous different blocks in parallel or in turn, and providing a minimal stream of values back out to indicate the result of the test.

Test speed (and thereby test cost) is improved by reducing the amount of I/O, and you can test the internal circuitry, at speed, without explicit access to every pin thanks to a dedicated test port and a healthy dose of internal multiplexing and test mode control.

But then comes the question of testing in the 3D package. Now you have two or more dice nicely enclosed in plastic, with access to only one of the dice. If the dice are considered to be completely independent of each other, then you have absolutely no way of accessing the unbonded dice. The dice obviously talk to each other – after all, that’s why they’re stacked together. But, without any testing forethought, those signals do nothing for test access.

The mechanisms for managing tests in a single die can be extended to multiple dice. The idea is to take the testing that was done on each individual die at wafer sort and repeat it – plus more – inside the package. Reuse is important: you don’t want to have to redo all your tests from scratch with a multi-die stack after developing them separately. Yet you can’t just apply the wafer sort tests directly on the packaged part since you aren’t accessing the pads on the hidden dice.

This means modifying your test structures so that the test port on the base die can be used to route signals to the other dice as well. Which means dedicating some TSVs for routing test signals between dice. Which means you had better take this into account when designing the individual dice to make sure you get the proper TSV allocations and routing.

There is still more monkeying that happens with the test signals at final test. For the base die, the test access circuitry at wafer sort simply provides test access to its own internals. At final test, it also has to manage the signals for the other dice. That involves different muxing and scan chain lengths and bypass modes. None of this is rocket science; it’s bookkeeping. But tedious, precise bookkeeping: miss one padding bit in a set of 10,000 bits of scanned data, and nothing will work. And it has to be designed into the die from the start; it won’t work as an afterthought.

This is why Mentor has recently announced their Tessent-3D product. It leverages the DFT technology they use for single dice, extending it for 3D ICs. To be clear, getting rid of the bad apples by tightening up wafer sort is more or less a new motivator for existing technology. It’s the ability of the tools to contemplate the management of tests among multiple dice that’s new.

Stepping back a bit, if you were to draw a logical block diagram of the total 3D IC, with no delineation of die boundaries, then there’s really nothing new. It might as well be one big chip. But the realities of how these things are conceived and put together, coupled with the need to test both individually at wafer sort and together at final test, make it practical to handle via a product dedicated to 3D ICs.

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