This whitepaper describes various memory interface and controller design challenges and the 7 series FPGA high-performance solution that achieves a 1.866 Gb/s DDR3 data rate for Virtex®-7 and Kintex™-7 FPGAs.

FPGA-based systems frequently require an external memory interface to buffer data that exceeds the capacity of the FPGA’s internal memory. This memory interface can often dictate overall system performance because it must provide sufficient read/write bandwidth to keep up with the flow of data into and out of the FPGA.

This I/O performance requirement translates into the need for higher memory interface bandwidths with each new generation of FPGA products. In addition to higher performance, the memory interface solution also needs to be flexible and easy to implement. In many ways, the memory controller and interface design determines the capability of the overall system.

Click here to download this whitepaper.