As system bandwidths continue to increase, memory technologies have been optimized for higher speeds and performance. The next generation family of Double Data Rate (DDR) SDRAMs is the DDR3 SDRAM. DDR3 SDRAMs offer numerous advantages compared to DDR2. These devices are lower power, they operate at higher speeds, offer higher performance (2x the bandwidth), and come in larger densities. DDR3 devices provide a 30% reduction in power consumption compared to DDR2, primarily due to smaller die sizes and the lower supply voltage (1.5V for DDR3 vs. 1.8V for DDR2). DDR3 devices also offer other power conservation modes like partial refresh Another significant advantage for DDR3 is the higher performance/bandwidth compared to DDR2 devices due to the wider pre-fetch buffers (8-bits wide for DDR3 compared to 4-bits for DDR2), and the higher operating clock frequencies. However, designing to the DDR3 memory interfaces also becomes more challenging. Implementing a high-speed, high-efficiency DDR3 memory controller in a FPGA is a formidable task. Until recently, only a few high-end (read: expensive) FPGAs supported the building blocks needed to interface reliably to high speed DDR3 memory devices. However, a new generation of mid-range FPGAs now provides the building blocks, a high-speed FPGA fabric, clock management resources and the I/O structures needed to implement the next generation DDR3 memory controllers. This white paper examines the design challenges, and how one particular FPGA family, the LatticeECP3, can facilitate DDR3 memory controller design. 

System bandwidth requirements continue to grow exponentially. As prices for DDR3 SDRAMs fall, DDR3 SDRAMs will be more widely adopted in networking applications. These increasing system bandwidth requirements are pushing memory interface speeds while costs continue to be driven down. Facilitating the design of robust high-speed memory interfaces in a mid-range FPGA was a principal goal of the Lattice ECP3 family of FPGAs. The dedicated yet flexible DDR capabilities of the ECP3 mean that designers now have a cost-effective solution for next-generation memory controller needs. The LatticeECP3 DDR3 primitives, coupled with the Lattice DDR3 memory controller IP core, significantly reduce the complexity of DDR3 memory interfaces and facilitate quicker time-to-market for next generation system designs implementing DDR3.