Like its predecessor, the Peripheral Component Interconnect (PCI), PCI Express is becoming a ubiquitous system interface. Unlike PCI, PCI Express adopts a Serializer/Deserializer (SERDES) interface to provide users with the scalability required for future applications. As system bandwidths increase, more applications are moving to SERDES-based interfaces like PCI Express. In the past, ASICs or ASSPs typically have been used to implement next generation interface solutions. ASICs and ASSPs were popular choices because they provided a low cost, low power design solution. However, several new FPGAs families now offer very attractive options to designers. FPGAs provide an extremely flexible platform without the long lead times and large NREs typically associated with ASICs or the inflexibility of ASSPs. Newer generation FPGAs with embedded SERDES, like the LatticeECP2M and the LatticeECP3 devices, offer designers an extremely rich, high value programmable architecture, while also offering a low cost, low power solution for serial interfaces. The same FPGAs can be used to support a variety of serial protocols like PCI Express, Gigabit Ethernet, SGMII, XAUI, Serial RapidIO, and others, providing a single FPGA platform for multiple designs.

PCI Express is also becoming the interface of choice for control plane applications, replacing older parallel interfaces like PCI. Newer generation devices use one or more PCI Express links. In a majority of devices, the PCI Express core is implemented as a PCI Express endpoint. Designers often need to connect these devices to previous generation devices that have a parallel bus (e.g., microprocessors with parallel bus interfaces). Using a low cost, low power FPGA to bridge between PCI Express and a parallel interface provides designers the flexibility to solve this problem without exceeding their system cost and power budgets.