Reason #1 – Lower Power

Some people think that all RISC processors deliver about the same performance per clock cycle. This assumption is wrong for processor cores that have been customized for a specific application. By customizing the processor, designers can get a significant performance improvement for each clock cycle.

A designer can add custom instructions to a processor’s ISA, which will increase the processor core’s size, which in turn increases the processor core’s average power dissipation per clock cycle. However, is the new instructions dramatically cut the total clock cycles required to perform a given workload, then the total energy consumed (power-per-cycle multiplied by total cycle time) can be substantially limited.

Example: A 20% increase in power dissipated per clock cycle, offset by a 3x speed up in task execution, actually reduces energy consumption by 60%. This reduction in required task-execution cycles allows the system either to spend much more time in a low-power sleep state or to reduce processor’s clock frequency and core operating voltage, leading to further reductions in both dynamic and leakage power.