The PCIe-DMA base platform moves data between system memory and the FPGA. The data thus transferred, can be consumed within the FPGA, or forwarded to another FPGA, or sent over the backplane using a serial connectivity protocol such as the Aurora 8B/10B serial protocol. Similarly, data can be brought in to the FPGA from another FPGA or backplane through the Aurora protocol and sent to system memory for further processing or analysis. This enhancement retains the Ethernet operation as is and demonstrates PCIe-to-Ethernet and PCIe-to-Aurora bridging functionality.

This application note builds on the Spartan-6 FPGA PCIe-DMA-DDR3-GbE TRD by extending it to connect to the Xilinx proprietary Aurora 8B/10B serial protocol. Aurora is a scalable, lightweight, link-layer protocol that is used to move data across point-to-point serial links. It provides a transparent interface to the physical serial links and supports both framing and streaming modes of operation. This application note uses Aurora in framing mode.

The network path functioning as the network interface card remains the same. The memory path is modified to support packet FIFO over the Spartan-6 FPGA memory controller and integrating the Aurora 8B/10B LogiCORE IP, which operates through the packet FIFO.

This application note also provides directions on making modifications and incorporating Aurora 8B/10B IP in the Spartan-6 FPGA Connectivity TRD to  arrive at the design shown in the block diagram below. 

Figure 1: Spartan-6 FPGA Connectivity TRD

Authors:  Vasu Devunuri and Sunita Jain