The density of FPGAs has grown with each process node shrink. Compared to previous generations of FPGAs, the extra density, coupled with features such as reconfiguration, enables designers to add to or change the functionality of these devices. FPGAs provide the perfect platform for accommodating improvements and design changes in functionality because of the reconfiguration feature. However, for some applications such as the 100G-OTN muxponders, this full reconfiguration feature may not be good enough. Because the muxponder application requires changes in logic without disrupting the entire system and stopping the flow of data, a need for a partial reconfiguration feature comes into play. Altera® Stratix® V FPGAs support partial reconfiguration along with many other features to address the 100G-OTN muxponder application and other applications.
Introduction
Partial reconfiguration is the ability to reconfigure part of the FPGA while the rest of the device continues to work. The biggest benefit users can derive from this feature is reduced device count. Partial reconfiguration improves logic density by removing the need to implement functions that do not operate simultaneously in the FPGA. Using smaller devices or a reduced number of devices improves system cost and lowers power consumption. Important applications for this technology include reconfigurable communication systems and high-performance computing platforms.
In static random access memory (SRAM)-based FPGA architectures, all user programmable features are controlled by memory cells that are volatile and must be configured on power-up. These memory cells, also called configuration random access memory (CRAM), contain the functions of the logic cells, routing, power-up conditions of registers, I/O voltage standards, and various other aspects of the FPGA.
The configuration memory is programmed via a bitstream, which contains the instructions for the control block and all the data for the configuration memory. This bitstream is programmed into the FPGA through a host using one of various configuration schemes, such as the fast passive parallel (FPP) configuration FPP x16, or through any available communication protocol such as the PCI Express®(PCIe®), Serial RapidIO® and Gigabit Ethernet (GbE) standards.
An SRAM-based FPGA can be partially programmed with a partially-generated bitstream that contains the instructions for the control block and the data for the configuration memory. Supporting such functionality requires innovation in the silicon and intelligence built into the control block to handle the partially generated bitstream file. The FPGA fabric needs the ability to clear the existing functionality in the logic cells and program new functionality, while the rest of the fabric remains functional. Stratix V FPGAs offer this partial reconfiguration capability through innovation and intelligence built into the silicon fabric and Quartus® II software.
Applications
Partial reconfiguration is suitable for designs with many permutations that do not operate simultaneously and hence, can share the same resources on the FPGA. In such systems, one section of the FPGA continues to operate, while the other section is reconfigured for new functionality. Partial reconfiguration is suited for applications that require continuous operations because it provides an advantage over full reconfiguration with the ability to reconfigure a portion of the device.
Author: Ajay Jagtiani, Software Technical Marketing Manager, Altera Corporation
Ajay Jagtiani joined Altera in 2005 and is currently a member of the software marketing team. In this role, Mr. Jagtiani is responsible for planning timing closure and functional verification features in Altera’s Quartus II development software. He also provides support to third-party vendors working with Altera. Jagtiani has over 13 years of experience in the semiconductor industry, working at a variety of companies including Atrenta, Synplicity, and Lattice Semiconductor. He holds an MBA in financial analysis from the University of San Francisco, an MSEE from Stevens Institute of Technology, and a BSEE from Bombay University.
