Implementing digital signal processing (DSP) datapaths with different performance, precision, intellectual property (IP), and development flows is challenging and labor intensive. As more and more high-performance DSP datapaths are implemented on FPGAs, Altera has developed a complete DSP solutions portfolio at 28 nm to address these challenges and speed up the design cycle for FPGA-based applications. This white paper discusses the different components of this portfolio and how they come together to accelerate the implementation of a DSP design.
Introduction
Although signal processing is usually associated with digital signal processors, it is becoming increasingly evident that FPGAs are taking over as the platform of choice in the implementation of high-performance, high-precision signal processing. Accordingly, FPGA vendors are beginning to include hard multipliers and DSP blocks within their core silicon architecture. IP cores are also provided to assist traditional functions such as finite impulse response (FIR) and fast Fourier transforms (FFTs).
As a result, a wide range of applications are now relying on FPGAs as the key signal processing platform. These applications, shown inFigure 1, share one thing in common—the performance requirements exceed the capabilities of a traditional programmable digital signal processor.
Figure 1. Different Applications Need Different Performance, Precision, IP, and Tools
These systems not only have different performance and precision requirements, but also different design and development flows. For example, video processing requires 9- to 10-bit precision, with some high-end designs needing a 16-bit color depth. These designs are generally created in a HDL design flow, with video- and image-processing IP functions increasingly utilized to speed up the development flow. On the other side of the spectrum, military radar designs require the highest DSP performance and floating-point precision to get the highest dynamic range. Many of these designs are modeled in the popular MATLAB and Simulink tools, along with floating-point functions that are optimized for the FPGA architecture.
Altera’s Total 28-nm DSP Portfolio
The biggest challenge faced by FPGA vendors is in providing a complete DSP solution portfolio—one that not only includes a DSP silicon architecture that is configurable, but also a range of tools, IP, and building blocks that can help designers to quickly and efficiently complete the implementation of their algorithms. To support the 28-nm Stratix® V FPGAs, Altera offers a total DSP portfolio, which, as illustrated in Figure 2, comprises a variable-precision DSP architecture, the DSP Builder Advanced Blockset, a video design framework, and a comprehensive suite of floating-point IP.
Figure 2. Industry’s First ‘Total’ DSP Portfolio
Variable-Precision DSP Architecture
The basic principle behind Altera’s DSP solutions portfolio is the recognition that one size does not fit all, that it is necessary to understand the diverse needs and preferences of customers in the design and development environment. Signal processing applications have different precision requirements and different precision levels at different stages of the signal processing data-paths. For example, video broadcast applications can efficiently use multipliers ranging from 9×9 to 18×18.
Author: Suhel Dhanani, Sr. Manager, DSP Marketing, Altera Corporation
Mr. Dhanani is responsible for DSP product marketing. He has over 15 years of industry experience in semiconductors, and has completed a graduate certificate in Management Science from Stanford University and holds MSEE and MBA degrees from Arizona State University.
