Campbell, CA – June 10, 2010 – Silicon Frontline Technology, Inc. (SFT), the silicon-proven, full- chip, field-solver company, announced today that its F3D (Fast 3D) parasitic extraction software for post-layout verification, has been selected as part of TSMC’s 28 nanometer (nm) Analog and Mixed-Signal (AMS) Referenced Flow 1.0. F3D was chosen because it offers parasitic extraction with guaranteed accuracy along with the capacity and performance to handle large nm designs.

“We are pleased to have the world’s leading foundry, TSMC, select our 3D extraction software for their 28nm AMS Reference Flow,” remarked Yuri Feinberg, CEO. “With F3D, TSMC’s customers can achieve guaranteed accuracy and take advantage of our full-chip capacity and exceptional performance.”

 “TSMC collaborates with select EDA suppliers like Silicon Frontline to get design toolsready for our most advanced semiconductor processes,” added Tom Quan, deputy director, design methodology and service marketing at TSMC. “Silicon Frontline’s 3D extraction software has been one of the first EDA tools to be included in our 28nm AMS Reference Flow.”

Last year, TSMC validated Silicon Frontline’s F3D product for 40- and 65-nanometer design technologies for its iRCX support.

The Importance of Guaranteed Accuracy, Performance

The demand for higher performance and reliability for designs targeting nanometer process nodes drives the need for parasitic extraction accuracy. Analog, AMS, and embedded memory designs require extraction software that delivers 3D field-solver accuracy, since small coupling capacitances can very often be the cause of failure.

Silicon Frontline’s post-layout verification software offers accuracy and high performance based on its proprietary and rigorous 3D technology to extract parasitics. Users specify the level of accuracy desired, net by net, at the block level or with regular expressions. In this way, the resulting parasitics are guaranteed correct within the specified accuracy.

Silicon-Proven Technology

Since Silicon Frontline’s introduction last year, the company’s 3D technology has been endorsed by the world’s leading foundries, its customers include eight of the world’s top 25 semiconductor companies and its software has been used to verify over 200 designs.

About Silicon Frontline

Silicon Frontline Technology, Inc. provides post-layout verification software that is Guaranteed Accurate and works with existing design flows from major EDA vendors. Using new 3D technology, the company’s software products improve silicon quality for standard and advanced nanometer processes. For more information please visitwww.siliconfrontline.com.For sales or general assistance, please emailinfo@SiliconFrontline.com or sft@marubeni-sys.com.

MOUNTAIN VIEW, Calif., June 10, 2010 – Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Samsung Electronics’ foundry business (Samsung Foundry) has successfully taped out its first 32 nanometer (nm) system-on-chip (SoC) design using Synopsys’ Galaxy(tm) Implementation Platform. Samsung Foundry selected the Galaxy Implementation Platform as one of its implementation solutions for its mobile application processor because the platform’s seamless integration enabled them to meet timing while minimising power consumption and adhering to the tighter design and manufacturing constraints imposed by a 32nm process. In addition, significant productivity benefits were achieved using in-design physical verification. Staying within the cohesive design environment of the Galaxy platform saved time and enabled Samsung Foundry to tape out on schedule.

“Synopsys enabled us to successfully tape out at 32nm on schedule and achieve first-pass silicon success,” said Dr. KM Choi, vice president, design technology team, system LSI, Samsung Electronics. “Using the Galaxy Implementation Platform allowed us to develop a scalable flow capable of fully addressing our design challenges. The effective integration of IC Compiler and IC Validator avoided many time-consuming iterations between physical implementation and verification. We have decided to deploy in-design physical verification with IC Validator for all our future IC Compiler-based 32 and 45nm designs.”

In-design technology provides a productivity boost over traditional flows by enabling physical verification during the physical design. The traditional approach of first implementing then verifying the design leads to many iterations between physical verification and implementation, which can result in significant schedule delays. Synopsys’ integration of IC Validator within IC Compiler allowed Samsung Foundry to optimise metal fills that were timing-aware and of signoff quality. The new approach saved time by avoiding unnecessary data transfers and eliminating costly iterations while producing a clean, error-free layout.

Samsung Foundry deployed the Synopsys DC Ultra(tm) synthesis solution with topographical technology and the DesignWare(r) library to accurately predict performance of the design during synthesis. The tight integration within the Galaxy platform reduced iterations between synthesis and layout. The IC Compiler MCMM capability was employed by Samsung Foundry to optimise across several scenarios while the Zroute technology within IC Compiler was used to generate DRC clean wires. Samsung Foundry used the PrimeTime(r) SI timing analysis solution together with accurate extraction from StarRC™ to analyse implications of on-chip variation and reduced wire spacing.

“The Galaxy platform consistently demonstrates the ability to handle the most challenging designs,” said Antun Domic, senior vice president and general manager of Synopsys’ implementation group. “Synopsys leads the effort to enable semiconductor manufacturers to achieve success in production designs at each successive technology node, as shown by the results of our close interaction with Samsung Foundry. Our large investment in R&D and collaborative approach are enabling our customers to achieve first-pass silicon success in such advanced nodes as 32nm. We look forward to continue our collaboration with Samsung Foundry to develop next-generation flows.”

Galaxy Implementation Platform

The Galaxy Implementation Platform is a comprehensive solution for cell-based and custom IC implementation. Galaxy accepts design intent in industry standard formats and generates a production-ready IC design in GDSII format. Galaxy RTL and physical implementation concurrently balance design constraints by performing intelligent tradeoffs between speed, area, power, test and manufacturability. Galaxy signoff engines accurately model complex physical interactions to ensure signal and power integrity. Coherent algorithms for parasitic extraction and timing produce correlated results.

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys’ comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, systems-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has more than 65 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com.

MOUNTAIN VIEW, Calif., June 10, 2010 – Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Samsung Electronics’ foundry business (Samsung Foundry) has successfully taped out its first 32 nanometer (nm) system-on-chip (SoC) design using Synopsys’ Galaxy(tm) Implementation Platform. Samsung Foundry selected the Galaxy Implementation Platform as one of its implementation solutions for its mobile application processor because the platform’s seamless integration enabled them to meet timing while minimising power consumption and adhering to the tighter design and manufacturing constraints imposed by a 32nm process. In addition, significant productivity benefits were achieved using in-design physical verification. Staying within the cohesive design environment of the Galaxy platform saved time and enabled Samsung Foundry to tape out on schedule.

“Synopsys enabled us to successfully tape out at 32nm on schedule and achieve first-pass silicon success,” said Dr. KM Choi, vice president, design technology team, system LSI, Samsung Electronics. “Using the Galaxy Implementation Platform allowed us to develop a scalable flow capable of fully addressing our design challenges. The effective integration of IC Compiler and IC Validator avoided many time-consuming iterations between physical implementation and verification. We have decided to deploy in-design physical verification with IC Validator for all our future IC Compiler-based 32 and 45nm designs.”

In-design technology provides a productivity boost over traditional flows by enabling physical verification during the physical design. The traditional approach of first implementing then verifying the design leads to many iterations between physical verification and implementation, which can result in significant schedule delays. Synopsys’ integration of IC Validator within IC Compiler allowed Samsung Foundry to optimise metal fills that were timing-aware and of signoff quality. The new approach saved time by avoiding unnecessary data transfers and eliminating costly iterations while producing a clean, error-free layout.

Samsung Foundry deployed the Synopsys DC Ultra(tm) synthesis solution with topographical technology and the DesignWare(r) library to accurately predict performance of the design during synthesis. The tight integration within the Galaxy platform reduced iterations between synthesis and layout. The IC Compiler MCMM capability was employed by Samsung Foundry to optimise across several scenarios while the Zroute technology within IC Compiler was used to generate DRC clean wires. Samsung Foundry used the PrimeTime(r) SI timing analysis solution together with accurate extraction from StarRC™ to analyse implications of on-chip variation and reduced wire spacing.

“The Galaxy platform consistently demonstrates the ability to handle the most challenging designs,” said Antun Domic, senior vice president and general manager of Synopsys’ implementation group. “Synopsys leads the effort to enable semiconductor manufacturers to achieve success in production designs at each successive technology node, as shown by the results of our close interaction with Samsung Foundry. Our large investment in R&D and collaborative approach are enabling our customers to achieve first-pass silicon success in such advanced nodes as 32nm. We look forward to continue our collaboration with Samsung Foundry to develop next-generation flows.”

Galaxy Implementation Platform

The Galaxy Implementation Platform is a comprehensive solution for cell-based and custom IC implementation. Galaxy accepts design intent in industry standard formats and generates a production-ready IC design in GDSII format. Galaxy RTL and physical implementation concurrently balance design constraints by performing intelligent tradeoffs between speed, area, power, test and manufacturability. Galaxy signoff engines accurately model complex physical interactions to ensure signal and power integrity. Coherent algorithms for parasitic extraction and timing produce correlated results.

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys’ comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, systems-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has more than 65 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com.