SANTA CLARA, CALIF. –– June 8, 2010 –– Oasys Design Systems today announced its multi-year strategic licensing agreement with Xilinx for Oasys’ revolutionary Chip Synthesis™ technology.

The companies are not disclosing terms of the agreement or details regarding Xilinx’s long-term plans for implementing the technology for field programmable gate array (FPGA)-based design.

“With programmable chip sizes growing and complexity mounting, it was clear we needed to look at a new generation of synthesis to support the needs of our customers,” says Vin Ratford, Xilinx’s senior vice president of worldwide marketing.  “We were immediately impressed with Oasys’ Chip Synthesis technology for its speed, capacity, performance and quality of results.”               

Paul van Besouw, Oasys’ president and chief executive officer, adds:  “It gives us a great deal of pride that Xilinx has chosen the Oasys technology to address the scaling of solutions for next generation programmable platforms.  Oasys currently provides a new generation of implementation platform for ASIC designers.  We will continue to focus in this area, and the unique partnership with Xilinx will bring benefits of our revolutionary technology to leading-edge FPGA designers as well.”

RealTime Designer™, based on Oasys’ Chip Synthesis technology, is the first design tool for physical register transfer level (RTL) synthesis of 100-million gate designs.  It synthesizes RTL code to placed gates in a single pass and in a fraction of the time traditional synthesis does.  A unique RTL placement feature eliminates unending design closure and iterations between synthesis and layout. 

Oasys will demonstrate RealTime Designer at the 47th Design Automation Conference (DAC) in Booth #202 June 14-16 at the Anaheim Convention Center in Anaheim, Calif. 

About Oasys Design Systems

Oasys Design Systems is a privately funded electronic design automation (EDA) software supplier with a revolutionary new platform called Chip Synthesis™, a fundamental shift in how synthesis is used to design and implement ICs larger than 20-million gates.  It has attracted the support of legendary EDA leaders and its RealTime Designer™ is in use at leading-edge semiconductor and systems companies worldwide.  Follow Oasys on Twitter at:  www.twitter.com/OasysDS. Corporate Headquarters is located at 3250 Olcott Street, Suite 120, Santa Clara, Calif.  95054.  Telephone:  (408) 855-8531.  Facsimile:  (408) 855-8537.  Email:  info@oasys-ds.com.  For more information, visit: www.oasys-ds.com

SANTA CLARA, CALIF. –– June 8, 2010 –– Oasys Design Systems today announced its multi-year strategic licensing agreement with Xilinx for Oasys’ revolutionary Chip Synthesis™ technology.

The companies are not disclosing terms of the agreement or details regarding Xilinx’s long-term plans for implementing the technology for field programmable gate array (FPGA)-based design.

“With programmable chip sizes growing and complexity mounting, it was clear we needed to look at a new generation of synthesis to support the needs of our customers,” says Vin Ratford, Xilinx’s senior vice president of worldwide marketing.  “We were immediately impressed with Oasys’ Chip Synthesis technology for its speed, capacity, performance and quality of results.”               

Paul van Besouw, Oasys’ president and chief executive officer, adds:  “It gives us a great deal of pride that Xilinx has chosen the Oasys technology to address the scaling of solutions for next generation programmable platforms.  Oasys currently provides a new generation of implementation platform for ASIC designers.  We will continue to focus in this area, and the unique partnership with Xilinx will bring benefits of our revolutionary technology to leading-edge FPGA designers as well.”

RealTime Designer™, based on Oasys’ Chip Synthesis technology, is the first design tool for physical register transfer level (RTL) synthesis of 100-million gate designs.  It synthesizes RTL code to placed gates in a single pass and in a fraction of the time traditional synthesis does.  A unique RTL placement feature eliminates unending design closure and iterations between synthesis and layout. 

Oasys will demonstrate RealTime Designer at the 47th Design Automation Conference (DAC) in Booth #202 June 14-16 at the Anaheim Convention Center in Anaheim, Calif. 

About Oasys Design Systems

Oasys Design Systems is a privately funded electronic design automation (EDA) software supplier with a revolutionary new platform called Chip Synthesis™, a fundamental shift in how synthesis is used to design and implement ICs larger than 20-million gates.  It has attracted the support of legendary EDA leaders and its RealTime Designer™ is in use at leading-edge semiconductor and systems companies worldwide.  Follow Oasys on Twitter at:  www.twitter.com/OasysDS. Corporate Headquarters is located at 3250 Olcott Street, Suite 120, Santa Clara, Calif.  95054.  Telephone:  (408) 855-8531.  Facsimile:  (408) 855-8537.  Email:  info@oasys-ds.com.  For more information, visit: www.oasys-ds.com