With high-speed 100-GbE communication network standards converging, switching functions play a key role in the smooth functioning of the Internet. The aggregated network traffic doubles every six months and grows in complexity as it is transported across multiple protocols, challenging the limits of current switch architectures. Because today’s single-chip-based architectures are unable to meet this demand for increased bandwidth and complexity, there is a need to develop efficient algorithms and switching architectures to meet the high-speed network requirements. Stratix V FPGAs enable hardware designers to integrate true 100-GbE components for next-generation switches and routers that ensure QoS while balancing the distribution of data through the system.
Introduction
Switching networks are used as intelligent interconnect structures for computer networks and high-speed 100-GbE networks. Historically, these interconnect networks were deployed independently in telephone, computer, and internet infrastructure networks.
Today’s communication networks are converging towards a common interconnect switching technology with the objective of a single interconnect network capable of distributed processing capability. Traditional telephony networks, based on time-division multiplexed (TDM) switching, are transitioning to Ethernet/IP packet-based switching networks. This transition has an impact on the switching function as Ethernet frames and IP packets have variable packet lengths that add further complexity to the buffering and segmentation of the switch. This evolution towards IP switching requires the support of existing networks and demands hybrid switches.
Hybrid switch fabric devices support different protocols, such as Ethernet, SONET, and TDM, and are even used for backplane switching. These devices must also support various interconnect protocols, such as SPI-4/-5.2, Interlaken, SRIO and XAUI, in addition to different encoding schemes, such as 8B/10B and 64B/66B. Inside the switch, these packets are stored in buffers and later segmented into different packet sizes based on the switch algorithm to obtain better overall network traffic efficiency.
Figure 1 shows a typical switch chassis consisting of a number of switch line cards connected to network processing units (NPUs) that are interconnected with a switch fabric. The data enters through an ingress processor, goes through the switch fabric, and leaves from the egress processor. The primary function of the NPUs is to inspect the arriving packets to determine their quality of service (QoS), perform any packet modification such as encapsulation—which is protocol dependent—and encryption/decryption to ensure network security.
Figure 1. Typical Switch Chassis
This switching architecture has an inherent memory limitation that does not meet the requirement for the packet queuing process. Even in the shared memory architecture, where switches contain a global memory to be shared across all the line cards for queuing purposes, the performance is directly scaled to the memory as the demand for bandwidth grows.
Because compensating for the memory challenges and redesign with a new line card using ASIC or ASSP platforms is an expensive proposition, designers are always looking for new cost-effective alternatives for their switch fabric architectures. One way to overcome this challenge is to queue the packets at the input stream, a method known as the input-queuing model.
Author: Rishi Chugh, Senior Product Marketing Manager, Altera Corporation
