Until recently, low power designs used a single voltage supply and a host of voltage control techniques such as power domains, power shutdown or power gating, and standby to reduce power consumption. However, process geometries are shrinking rapidly and power is not scaling well, posing a barrier to Moore’s law. Consequently, low power designers have adopted increasingly aggressive techniques such as using multiple supply voltages. Multiple supply voltages imply a design with blocks and cells featuring multiple supply rails, further compounding the already daunting task of verifying low power designs. Incomplete or improper verification of such designs leaves open the possibility of functional failures in silicon.
The Voltage-Frequency Dance
How do you decide on an operating voltage for a design? The question is relevant because voltage and frequency are often opposing requirements in a low power design. Reducing voltage brings about power reduction but has the undesirable effect of limiting the frequency of operation. The answer lies in the maximum targeted frequency of operation. The voltage supplied must be sufficient to allow the transistors to switch fast enough. If you use a single voltage supply for the chip, you end up choosing the lowest operating voltage that facilitates maximum performance, and the power characteristic of the design is limited by the target frequency of operation.
An elegant idea to cut power consumption but still keep the design humming at the desired frequency is to recognize that all parts of the design don’t need to operate at the target frequency. The chip architect recognizes that different functional units need to operate at different frequencies and partitions the design based on them. Now each of those partitions can operate independently at just the required voltage. This is the idea behind multi-voltage designs. It is the culmination of the voltage-frequency dance that results in better power performance for the chip while meeting the frequency requirements.
Power Architecture Choice Leads to Multi-Rail Cell Usage
Once you decide on an architecture that involves multiple voltages, you must ensure that each power domain is associated with a specified supply voltage. Signals crossing power domains operating at different voltages require their voltages be stepped up or down appropriately with level shifters. To do so, level shifters must have two supply rails: one driven by the source voltage and the other by the target voltage of the driven domain.
Even when multiple voltages are not involved in a design, low power architectures employing multi-rail cells may be used. To quickly wake up power domains that have been turned off, data is typically retained in retention registers. Retention registers retain the data when power to a domain is switched off, which implies that these registers must have an alternate power source.
Retention registers commonly have two power rails – one rail is used to power the register when the power domain is on, and the other to keep data when the power domain is switched off. Even when a single-supply design is just switched off, isolation cells that protect an on domain from the effects of being driven by a switched-off domain may be implemented with multiple rails to make the physical layout more area efficient. This means that even single voltage designs may have multi-rail blocks because of the need for retention and area efficiency.
Multi-Rail Verification Challenge
In a single-rail design, the verification challenge is to associate each output of a logic function to the value of the supply voltage. However, all the outputs are affected by the same supply voltage. By contrast, multi-rail cell designs require that verification must be aware of the particular supply voltage driving each output since not all outputs will depend on the same supply voltage. In the absence of such an association, verification results will be inaccurate. Bugs that would otherwise surface would go unnoticed and raise their ugly heads in silicon.
Multi-Rail Verification Solution
A well-architected verification solution must first provide a way to specify the association between logic and power pins at the cell description (library) level. Making this information part of the library description liberates designers to create the best possible low power designs without worrying about the intricacies of the power management cells. It also transfers the ownership of maintaining these libraries to the cell designers, which is usually a central library group in a large company or a 3rd party library vendor. Since the same cell library is used across multiple projects, having this information centralized reduces the possibilities of inconsistent databases, leading to more accurate information being available for verification tools to operate.
The second piece of the puzzle is chip-level information. Since power rails are used to guide power to these cells, the solution must then provide a way to bind the cell and block/chip level information and complete the associations between cell-level power pins and chip-level power rails.
Once the association has been made, static verification tools must be able to use this information to determine if there are improper or missing connections and report them. Dynamic verification tools have to comprehend the effect of multiple rails and resolve the logic values at the outputs depending on the voltage strength of each of the inputs. By definition, this can only be accomplished by a voltage-level aware simulator. Checks are needed as early as the RTL stage of the design but also need to be followed up as the design progresses through the synthesis and place and route steps.
The introduction of multiple supply voltages and multi-rail cells has made a complex verification problem worse. An ostrich approach to the problem will only result in functional failures in silicon. Rather, the entire verification infrastructure, starting with the way the information is properly captured to the way the database is built, needs to change in order to even attempt to build the correct solution. Low power verification tools require a facelift to make the proper associations between cell and chip-level information to detect bugs. Now more than ever, your chosen low power verification solution must have the right architecture to live up to the challenge of verifying multi-rail designs.
Krishna Balachandran is director of product marketing for low power verification products at Synopsys. He holds a master’s in computer engineering from the University of Louisiana and has completed the executive MBA certification program at Stanford University.