Any LogiCORE™ IP, Alliance Core, or other IP cores used in the design are configured for the Spartan-6 architecture. However, blocks intended for a different architecture (e.g., Virtex-5 FPGAs) can go through the same tools but do not yield the best results. Synchronous resets should be used in the RTL whenever possible because they are better suited for digital signal processing (DSP) and block RAM inference for Spartan-6 FPGAs. Synchronous resets make it possible for the synthesis tool to pack registers into DSP blocks and block RAM.

The number of logic levels is a good indicator of future performance before moving the design to place and route. Synthesis results should thus be checked to evaluate this number. Higher performance is enabled by fewer levels of logic between registers. Timing constraints should be used during synthesis because they enable more optimizations. To further improve synthesis, additional design approaches can be used, such as register balancing (retiming) or state machine optimizations. Refer to the synthesis tool documentation for more information about these additional design options.

The synthesis tool should be set up so that it reads the black-boxed netlists or IP cores by adding them to the synthesis project (use the read_cores option in XST). This could also improve performance by enabling logic optimizations around the black boxes.

The performance of Spartan-6 FPGA designs can be improved by leveraging performance options in the design tools (ISE software and SmartXplorer) and understanding the bottleneck(s) in the design. Using a faster speed grade device and optimizing the RTL are other simple and proven methods of improving design performance.