This white paper identifies the drivers behind the migration to 100G interfaces, and shows how to leverage FPGAs to implement this high-speed interface. The emerging 40GbE and 100GbE standards for data center and core network systems rely heavily on FPGAs to share those sectors with other protocol infrastructures. In addition to providing an unprecedented amount of resources such as logic, on-chip memory, and DSP blocks, Stratix IV devices are the only FPGA family to enable 40G/100G designs, which require 10G transceiver data rates with extraordinarily low jitter performance to meet high-speed design requirements.
Introduction
Using recent technological advancements, the current generation of FPGAs has the bandwidth, high transceiver count, and ability to support multiple protocol standards on a single device. Telecommunication equipment manufacturers-focused on developing the next generation in bridging applications and switching solutions for 40GbE and 100GbE-are the emerging target market segment for FPGAs, which can meet the high speed data rates and bandwidth requirements.
The emerging 40GbE and 100GbE standards for data center and core network systems rely heavily on FPGAs to share those sectors with other protocol infrastructures. (These include Fibre Channel, Infiniband, and SONET for more bridging and data aggregation types of application.) As LAN speeds increased to a gigabit, the most cost-efficient networks embraced Ethernet as the primary data link protocol, which could be satisfied by ASSPs and FPGAs. But as LAN, SAN, and MAN speeds surpass 10G, the most cost-efficient networks are embracing multiple data link protocols, which must use multiple ASSPs or deploy FPGAs as bridging devices to provide cost-effective
solutions.
Meeting the 40G/100G Requirements
To address the 40G/100G requirements, FPGAs have evolved over the last few process generations. At the 130-nm process nodes, FPGAs only supported up to 3.125 Gbps, while today’s 40-nm process nodes support data rates beyond 10 Gbps. Altera Stratix IV GX FPGAs have up to 32 embedded transceivers supporting data rates from 600 Mbps to 8.5 Gbps, plus an additional 16 transceivers supporting data rates from 600 Mbps to 6.5 Gbps. The transceivers include both a PCS and a PMA, which enable Stratix IV FPGAs to implement standard and proprietary protocols. Figure 2 shows a diagram of the Stratix IV GX transceiver block.
Moving to smaller process geometries allows for greater system integration in a chip because the FPGA densities roughly double from one process generation to the next. While increasing the feature set of the FPGA is important, being able to simultaneously meet leading-edge system performance requirements while minimizing power is extremely important.
Author: Rishi Chugh, Product Marketing Manager, High-End Device Marketing
