— LatticeECP3-150 FPGA is Ideal for High-volume, Low-cost 3G Basestation Designs —
HILLSBORO, OR — NOVEMBER 16, 2009 — Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced that the LatticeECP3™-150 FPGA, the highest-density device in its award-winning high-value, low-power ECP3 mid-range FPGA family, has been fully qualified and released to volume production.
The ECP3-150 device features a DSP capacity of 320 18×18 multipliers, 6.8 Mbits of memory and up to sixteen 3.2Gbps SERDES channels, making it ideally suited for highly complex and integrated Wireless Remote Radio Heads (RRH) such as MIMO-based RF antenna solutions. The ECP3-150 FPGA also provides Wireline Access developers with unprecedented high-density, low-cost, low-power Ethernet, SONET and PCI Express solutions, with the lowest cost points and power footprints in the FPGA industry. “With the production release of our ECP3-150 device, our customers can implement even more complex designs for wireless and wireline access and still benefit from the device’s low power and economy,” said Shakeel Peera, Lattice Marketing Director for SRAM FPGAs.
A range of intellectual property (IP) cores, including Crest Factor Reduction (CFR), Digital Pre-Distortion (DPD), CPRI, OBSAI, Serial RapidIO, XAUI, SGMII/Gigabit Ethernet, PCI Express, SMPTE for serial connectivity, FIR filters, FFT, Reed-Solomon encoders/decoders, CORDIC, CIC, NCO for DSP functions and several others for memory interfaces and connectivity, are available from Lattice and its partners to enable customers to develop time-to-market solutions.
About the LatticeECP3 FPGA family
The award-winning LatticeECP3 FPGA family is comprised of five devices that offer standards-compliant multi-protocol 3G SERDES, DDR1/2/3 memory interfaces for low cost FPGAs and high performance, cascadable DSP slices that are ideal for high performance RF, baseband and image signal processing. Toggling at 1Gbps, the LatticeECP3 FPGAs also feature the fastest LVDS I/O available in a mid-range FPGA family, as well as embedded memory of up to 6.8 Mbits. Logic density varies from 17K LUTs to 149K LUTs with up to 586 user I/O.
With these features, the LatticeECP3 FPGA family is ideally suited for deployment in high volume cost- and power-sensitive wireless infrastructure and wireline access equipment, as well as video and imaging, applications. For more information about the LatticeECP3 FPGA family, please visit www.latticesemi.com/products/fpga/ecp3
Design Tool Support
The LatticeECP3 FPGA family is supported by the ispLEVER® design tool suite, version 8.0. The ispLEVER design tool suite is the flagship design environment for the latest Lattice FPGA products. It provides a complete set of powerful tools for all design tasks, including project management, IP integration, design planning, power analysis, place and route, on-chip logic analysis and more. The ispLEVER tool suite is provided on CD-ROM and DVD for Windows, UNIX or Linux platforms. Synopsys’ Synplify Pro advanced FPGA synthesis is included for all operating systems supported, and Aldec’s Active-HDL Lattice Edition simulator is included for Windows.
Lattice devices are also supported by Mentor Graphics ModelSim SE and Precision RTL synthesis and the full versions of Synopsys Synplify Pro and Aldec Active-HDL.
Pricing and Availability
LatticeECP3-150 devices are available now in two low-cost wirebond packages (672 fpBGA and 1156 fpBGA). Prices for the LatticeECP3-150 in the 672 fpBGA package in 25K unit volumes start at $75. The LatticeECP3-70 and LatticeECP3-95, which were production released in February, are priced at $35 and $50, respectively, in 25K unit volumes.
About Lattice Semiconductor
Lattice is the source for innovative FPGA, PLD, programmable Power Management and Clock Management solutions. For more information, visit www.latticesemi.com
