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Decisions, Decisions, and Threads

The whole way through creating your SoC you are faced with decisions. Some of the hardest decisions, since they are the most difficult to change if they are later seen as sub-optimal, are those made at the architectural level. How do you assign the tasks that you need in order to produce the performance you want, at a reasonable cost in IP licences, silicon real estate, power consumption, and end product performance? For this part of the application, we really require the number crunching of a DSP, while over here we want the flexibility of running an OS, say Linux, and maybe also have an RTOS to cope with critical areas. It would be great to add some co-processors here to handle specific tasks, while that particular activity would be better run on a general-purpose processor.

Having spread the tasks and assembled different processors, how do you develop the software? How do you get things working together, and how can you ensure that any processor is working efficiently, not stalled by context switching in the OS or by multi-cycle memory latencies?

And all this under the normal pressures of getting the product to market in the right time-scale and with the resources you have available.

Hey – you really earn your money, don’t you?

However, some people I saw a few days ago think they may have something to help you.

If you are working with graphics or video you probably already know Imagination Technologies and their PowerVR graphics processing unit (GPU) IP cores and their PowerVR video IP cores. (If you have ever used an iPhone, you have used PowerVR graphics.) Within these cores, Imagination has used, amongst other techniques, multi-threading techniques with hardware context switching to get the maximum performance on the screen. And now they are introducing META, a family of three 32-bit processor cores that uses a multi-threaded architecture to provide processing and DSP in a single device.

It is a bit misleading to say “now they are introducing” since the company has been using META cores in design platforms and in SoCs that they have designed for other people for some years now and are claiming that “tens of millions” have been shipped.

This relatively laid-back approach to a new product introduction is fairly typical of the way the company works. They have to think about the way in which the consumer market will be operating anything up to ten years down the road. The cycle is that Imagination has to identify a need, then create and validate the IP to meet that need. Then the company has to sell the idea to a silicon company, which in turn designs and builds the SoC to meet the need. This is then sold to, say, a consumer product company, which, in its turn, develops a product and sells it to the customers. If everything goes right, the customers then buy the product by the truckload. This has been the case with the company’s ENSIGMA UCCP230 Receiver IP. Through a licence with Frontier Silicon, Imagination IP is at the heart of seven out of ten DAB digital radio receivers, and Imagination has other licensees in the digital radio field. (DAB is a major standard for digital terrestrial radio. It is in wide use in Britain (analogue signals are already being turned off), and more advanced standards based on DAB, such as DAB+ and DMB, which are addressed in firmware by the UCCP230, are taking off around the world. 

While admitting to going down one or two blind alleys in the guessing game, Imagination has built its success on serving various aspects of what Tony King-Smith, VP Marketing, likes to call “the Apple effect.” This is not just shiny plastic boxes but stunning screens that are driven by the advanced graphics IP from Imagination!

So how will Imagination manage to elbow into the already very crowded market for processing cores? Firstly, King-Smith believes that they are already established as a safe choice for many designers. They have licensed IP to virtually all the big boys in silicon (Freescale, Intel, NEC, NXP, Renesas, Samsung and TI are just some of their customers) and lots of smaller ones. It is these licenses that have pushed it to fourth place in Gartner’s list of world revenues for IP in 2008.  So choosing a processor from Imagination should not be a leap of faith. (Slightly off topic – with ARM, that makes two British IP companies in the top four!)

Secondly, the processor is established. It is, as we have said, already shipping in volume, and it has a growing eco-system of IDE, debugging, instruction sets, and operating systems.

And thirdly, the processor is different – it brings multi-threading and parallel processing into the SoC in a new and powerful way.

Multithreading is not new: it has been used at the OS level, particularly for RTOSs, for many years. It is not even new at the hardware and IP core level: MIPS has been talking about it for some years. But Imagination thinks META is something different, built from the ground up for multi-threading.

Looking at the top-end META HTP core, it has four threads, each of which can be seen effectively as a separate processor. So a single META processor can act as four different processors working in parallel, perhaps with one running Linux and another working as a DSP and so on. Threads are configured at synthesis, so that, for example, the DSP features are implemented only when needed. DSP features include a VLIW-like instruction template, configurable DSP RAM, multiple data types, and private registers for each DSP thread.

As threads operate in parallel, there is no need for context switching.  This means more efficient use of the processing capability. Also, the processor can go on running other threads if one has to wait for memory. Superthreading means that threads can run simultaneously, as long as they don’t want the same resources, so every cycle sees one or more threads executing, again depending on which resources the thread wants to use. There is an Automatic MIPS Allocation (AMA) function, which controls allocation of resources to a thread, letting some run in background while others, say real-time threads, have immediate access to system resources. Low-level clock gating, controlled by thread and resource scheduling, allows unused resources to be turned off cycle-by-cycle, reducing power consumption.

A coprocessor interface provides up to eight ports so that thread operations can be synchronised with other hardware functions, and of course there is a Memory Management Unit (MMU). The HTP also has an optional floating point unit. The HTP data sheet shows 650 MHz in 65nm and claims 1610 DMIPS.

Alongside the META HTP is the META ATP, built for less demanding applications, running at only 250 MHz for 525 DMIPS, again in 65nm. It lacks the FPU option but otherwise has pretty much the same feature set.

The third core in the family is a single-threaded META (META MTX) for applications where silicon footprint and power consumption are significant constraints. It can operate from a single memory macro, and Imagination’s spec sheet shows 220 DMIPS in a 65nm process. It has only two coprocessor ports.

Imagination’s CODESCAPE development tools and IDE are used for all cores from silicon through SoC to end-product for software development and de-bugging. The suite is PC based and communicates with the target device in a development platform through a JTAG port. The tools, like the cores, are already well deployed. Included in the bundle is the CODESCAPE IDE; GNU ANSI C/C++ compilers; an assembler, library tools, and a linker; source-level debugger and a choice of intelligent debug adapters; META virtual target software simulators; DA-Script; and Application Post-Mortem Debugging, which, after a crash, will dump and restore context and memory.

Thread assignment is first implemented by making decisions at silicon synthesis, and then a load-link tool assigns software to threads.

RTOS support includes Embedded Linux, ATI Nucleus, Imagination’s own MeOS, iTRON and Tao Intent.

META cores are fully synthesisable and are delivered as HDL.

So that’s all the technical stuff. Multi-threading and parallel processing doesn’t mean Intel architectures and Core-Duo: what they should mean is improved throughput and greater control. And the Imagination approach, by putting the parallelisation in the hands of the developer to function at a machine/application level, removes many of the issues that occur when trying to parallelise a single application.


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