feature article
Subscribe Now

Locking Down Power

Altera Rolls Out Cyclone III LS

We’ve talked a lot in the past about the process node tango danced by the two largest FPGA companies. With each step, one leads and the other follows – usually with a twist. Unlike the traditional tango, however, we often have the lead changing with each subsequent move – a scheme certain to confuse most dance fans, but a situation that makes the FPGA market far more interesting. Also, unlike in the traditional tango, both dancers are doing their dead-level best to knock the other one off their feet. That makes things really exciting – from our perspective, at least.

Let’s review the normal steps, then see how the dance is progressing.  

Cue music:  Let’s go with Astor Piazzola’s “Libertango”…

five… six… seven… eight…

1998 – Xilinx launches “Spartan” – the first low-cost FPGA family.  Altera hasn’t heard the music start and is still in the dressing room adjusting wardrobe.

1999 – Xilinx takes the second step with widespread deployment of Spartan-II.

2002 – Altera hears the music, runs out onto the floor, and steps squarely on Xilinx’s toe with the introduction of 130nm Cyclone.  Xilinx trips, falls down and twists an ankle.

2003 – Xilinx struggles back to its feet and takes a big gamble, launching the Spartan-3 90nm before their high-end Virtex-4 devices.  It was probably much easier to bring up the smaller, simpler, low-cost device than the big, complex, high-end family.  Plus, the smaller size of the die means more die per wafer and correspondingly higher yields.  The gambit works pretty well, and Spartan-3 starts recovering some market share in the low-cost FPGA space.

2003 – Altera spins around with a flare and executes a “Gancho” step, launching the 90nm Cyclone II.  Now we are once again at parity on process node, and Altera has had a chance to read Xilinx’s data sheet before announcing their own.  Xilinx makes a substitution, sending the silicon design team to the trainer for a knee-wrap.  Xilinx marketing takes over and works to counter Altera’s move.

2007 – After a few years of parity, the music speeds up again.  Altera raises the ante and launches the 65nm Cyclone III family.  Xilinx’s design team apparently has gotten lost on the way back from the medic, and marketing is left alone to defend the aging Spartan-3 line against the newer generation Cyclone III.  It doesn’t go so well.  They call engineering for backup.  The phone line has been disconnected.  Scrapping together a small team, Xilinx marketing re-spins, re-names, re-fines, stacks die, re-prices… basically kicking up as much dust as possible so the judges won’t see what’s actually happening on the dance floor.

2009 – Xilinx Spartan engineering has apparently been located in a small cafe in Buenos Aires, where they’ve been practicing hard on the dance.  They fly back to the venue and boldly take the floor with 45nm Spartan-6 (and some spiffy new shoes) – this time, in concert with their 40nm Virtex-6 family.

This week – learning from Xilinx’s Spartan-3 experience, Altera must now defend against a new line at a more advanced process node.  Customers want lower power, design security, and higher density in their low-cost FPGAs.  Altera quickly responds, re-working their existing 65nm Cyclone III family to produce Cyclone III LS.  Luckily, they invited engineering.

Cyclone III LS is not just a re-marketed version of the existing family.  Yes, it is still on the same 65nm process as its older siblings, but it has significant new capabilities that warrant a look.  First, the capacity has been bumped to 200K logic elements.  That’s a big deal – clearly in the size range of the bigger high-end devices of just a couple of years ago.  For example, the company’s 90nm Stratix II FPGAs topped out at 180K.  Xilinx’s newly announced 45nm Spartan-6 family only goes up to around 150K.  

On top of the huge (for a low-cost FPGA) capacity, Altera has added two more important features to the line – low power operation and security features (hence the LS designation).  Don’t be confused by the seeming similarity of these designations to devices like Actel’s flash-based FPGAs.  Actel’s devices have far lower density, far lower power consumption, and dissimilar security strategies.  The taglines may sound the same, but you’ll probably never be choosing between them for the same socket.  

The marketing makes things even more confusing, of course.  Altera claims these are the “lowest power FPGAs with security.”  This is wrong.  The specification they cite is “200K LEs and 0.25W static power.”  That is spectacularly low static power for a high-capacity SRAM FPGA, but it is far from the lowest static power for an FPGA with security features.  That title would have to go to Actel’s (much, much smaller) devices with static power consumptions in the microwatts – two or three orders of magnitude less power.  What Altera should be directing our attention to is that this is amazing performance for a device in the “low-cost” category – and it has the capacity of a full-blown high-end FPGA.  

In comparing Cyclone III LS to high-end FPGAs, there are, of course, reasons it isn’t a high-end device.  Altera has used a low-power fabrication process, so you won’t see the kind of performance a high-end device can give.  You won’t find SerDes multi-gigabit transceivers, and you’ll find correspondingly smaller allocations of resources like memory and DSP cores.  

The devices have quite a robust set of security features, however.  The bitstream is encrypted by 256-bit AES, the JTAG port can be locked down, preventing readback, an active clear function allows the FPGA to be zeroed out in the event of a detected attack,  and CRC allows us to monitor for configuration changes.  Here’s how it works:  Your encryption key is stored in super-secret locations on the FPGA, and that encryption key is used to load the configuration bitstream from flash.  The JTAG port is locked down to prevent active readback of the configuration.  A set of tamper detection features kicks into gear, and if tampering is detected, the device is zeroed out.  Aha! you say – what if the attacker interrupts the clock line, freezing the device before the anti-tamper sequence can start?  Well, they thought of that, too – the device has an uninterruptible on-chip oscillator that keeps the clock ticking so the system can deploy its protective shutdown defense.  While no security scheme is un-breakable, the bad guys will have to be pretty determined, patient, and well funded to get through these defenses.

For applications where reliability is as important as security, Cyclone III LS also has a clever set of features to enable single-chip design redundancy.  You can physically partition your design into multiple separated design areas and run redundant copies of your circuit on a single chip.  This is useful for applications where there is concern about radiation events like single-event upsets (SEUs), where a wayward neutron can flip a bit of configuration logic and change the design of your circuit on the fly.  Design separation allows the “good” half to keep on ticking while you worry about how to fix the bad side.  This design style isn’t automatic, but Altera is supplying a nice set of app notes that will walk you through the basics.

We’ve always contended that the line between high-end and low-cost FPGA families would grow ever-blurrier.  Cyclone III LS has strengthened our belief.  While both big FPGA companies still propagate two brands each for low-cost and high-end FPGAs, the overlap between those families and the diversity within those families will probably make the branding become more and more irrelevant.  Only time will tell.

Leave a Reply

featured blogs
Dec 4, 2023
The OrCAD X and Allegro X 23.1 release comes with a brand-new content delivery application called Cadence Doc Assistant, shortened to Doc Assistant, the next-gen app for content searching, navigation, and presentation. Doc Assistant, with its simplified content classification...
Nov 27, 2023
See how we're harnessing generative AI throughout our suite of EDA tools with Synopsys.AI Copilot, the world's first GenAI capability for chip design.The post Meet Synopsys.ai Copilot, Industry's First GenAI Capability for Chip Design appeared first on Chip Design....
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....

featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

featured paper

Power and Performance Analysis of FIR Filters and FFTs on Intel Agilex® 7 FPGAs

Sponsored by Intel

Learn about the Future of Intel Programmable Solutions Group at intel.com/leap. The power and performance efficiency of digital signal processing (DSP) workloads play a significant role in the evolution of modern-day technology. Compare benchmarks of finite impulse response (FIR) filters and fast Fourier transform (FFT) designs on Intel Agilex® 7 FPGAs to publicly available results from AMD’s Versal* FPGAs and artificial intelligence engines.

Read more

featured chalk talk

What are the Differences Between an Integrated ADC and a Standalone ADC?
Sponsored by Mouser Electronics and Microchip
Many designs today require some form of analog to digital conversion but how you implement an ADC into your design can make a big difference when it comes to accuracy and precision. In this episode of Chalk Talk, Iman Chalabi from Microchip and Amelia Dalton investigate the benefits of both integrated ADC solutions and standalone ADCs. They discuss the roles that internal switching noise, process technology, and design complexity play when choosing the right ADC solution for your next design.
Apr 17, 2023