Many project teams move from ASICs to FPGAs to avoid high NRE costs, and to reduce the risk of re-spin and shorten time-to-market. But while FPGA technology offers these advantages, the development process itself requires equal attention. In fact, some ASIC/ASSP proponents argue that a large part of the design cost is incurred during the development phases including architectural exploration, design, and verification, thereby reducing the cost savings and time-to-market benefits of switching from ASICs to FPGAs.
For this reason, executives and project managers need to carefully consider their concept-to-PCB development approach. Is the process predictable, well integrated, and consistent from project to project? Does it allow for flexibility to move from one FPGA vendor to another as project requirements change? These are methodology and tool flow questions, and they impact the bottom line. In a down economy such as today’s, design teams are expected to cut costs yet still release innovative (i.e., “increasingly complex”) products and to finish their projects on time. If system houses want to truly leverage the benefits of FPGAs, they have to think about how their tools and methodologies help them minimize cost, mitigate risk, and shorten time-to-market.
Minimizing Cost
Development Cost
As development budgets shrink, companies are looking for creative ways to spend less. Tool cost is a likely target. There are multiple tools and approaches available for FPGA design and implementation today—some from electronic design automation companies (EDA) and others provided by FPGA vendors.
Tools supplied by FPGA vendors are free or nearly free, so adopting them might seem like the right approach when budgets are tight. Yes, these tools are free… but they are not without cost. Companies who decide they can save money by using vendor tools might end up paying more over the long term. It is no secret that the “free” tool business model tends to lock users into a specific FPGA vendor’s silicon. Switching to another device means investing significant engineering time to learn new tools and re-target the design using a new flow. Since time is money, the extra effort translates into greater development cost.
EDA vendors, on the other hand, can offer FPGA vendor-independent solutions that port across most, if not all, FPGA vendors. With vendor-independent ESL, IP re-use, verification, synthesis, and PCB flow, designers have no need to learn a new tool set and can objectively select the device that best fits their project needs as opposed to being influenced by prior tool choices. This flexibility is critical to system houses that want to remain competitive. FPGA vendors compete vigorously with each other on price, capacity, speed, functionality, and power. This is of course good for their customers, who rely on FPGA vendors’ competitiveness to ensure that they, in turn, roll out the most competitive FPGA-based products. By betting everything on one FPGA vendor, companies can lose their freedom of choice just when they need it most. Though EDA tools are not free, the tools usually make up only a small part to the overall project budget when their cost is spread across multiple projects.
Production Cost
A high quality, vendor-independent approach can also translate into lower production cost. With leading-edge synthesis from an EDA vendor, customers can achieve the best QoR to fit into the cheapest device. Without committing to a specific FPGA on the front end, a user can target the design to multiple devices and objectively select the least expensive device that still meets design requirements. This demands a vendor-independent synthesis tool that aggressively pursues superior QoR for all major FPGA vendors. With vendor-independent design tools and methodologies, companies can not only select the most cost-effective device but can also find the best deal on the market without feeling pressured to work with any specific FPGA vendor.
Mitigating Risk
While selecting an FPGA vendor-independent approach reduces the risk of device lock-in, project teams are still tasked with selecting the right tool provider. Not all EDA offerings are created equal, therefore system houses have to consider their EDA vendor not just as a tool provider but also as a long-term business partner. Along with a complete solution, the chosen EDA vendor should have a substantial track record of commitment to the FPGA development community. A company should invest in a vendor’s FPGA tools and methodologies only if it is confident that its partner is in it for the long haul.
Shortening Time to Market
Time is money not only in terms of R&D expense, but also in terms of meeting a product’s market window. The reprogrammable architecture of FPGAs addresses this in part, but design methodology has an equal impact. If the development process is haphazard, different for each FPGA vendor, and based on loosely integrated point tools, the design cycle becomes unpredictable. When companies meet the market window for some projects and miss it for others, they cannot confidently forecast the success of their product lines.
While several EDA companies offer FPGA tools, it is important to partner with a vendor that offers quality tools and complete, well-integrated solutions that use advanced methodologies to span the process from system level design to PCB development. Such a comprehensive flow not only ensures consistent results and predictable schedules, but also provides a single point of support for quick problem resolution. It is a winning combination that ultimately shortens the design cycle.
Conclusion
The ASIC-to-FPGA conversion rate is expected to increase in the current economic environment, and system houses must recognize there’s more to an FPGA strategy than re-programmability; more than achieving shorter lead times and avoiding mask-set costs. A company should consider its tool provider as a long-term development partner and select one with a proven track record of commitment to FPGA development. As evidence of this commitment, the provider should have a complete solution that supports advanced design creation, verification, synthesis, and PCB development methodologies that will help reduce cost, mitigate risk, and shorten time-to-market.
