Parasites are generally not perceived as a good thing. They benefit at the expense of something else. There’s none of the quid pro quo associated with a symbiotic relationship. There’s a clear winner and a clear loser. The question is whether or not the host can muster the wherewithal to withstand the parasite, even if the hanger-on can’t be shaken off completely.

Semiconductor ICs suffer from parasites. They’re the uninvited capacitors and resistors and their ilk that attach themselves to brilliantly conceived circuits, typically challenging the mettle of the designers that would minimize the role of the parasite in the operation of the circuit. Such a parasitic component might well be surprised, therefore, when, in a deftly executed aikido maneuver, the strength of the parasite is used against itself, and, in fact, in favor of the circuit.

In another of our ongoing series of discussions of memory structures riding to the rescue as today’s tried and true storage cells see their futures dimming, we look at a memory cell that hijacks the functioning of a parasitic transistor within an MOS transistor. The company developing this cell, Innovative Silicon, has dubbed the memory Z-RAM.

Z-RAM belongs to a class of memory cells referred to as “floating body” memories. As we may recall, the body of an MOS transistor is, basically, that part of the transistor that isn’t the source or the drain. Under the right conditions – when the transistor is turned on – that part of the body right under the gate becomes the channel.

With your standard garden-variety wafer, the body is part of the bulk of the silicon wafer. It’s more or less what the wafer was before sources and drains were implanted at the surface. And typically the bulk of the wafer – and hence the body – is connected to some potential like ground.

If, on the other hand, you grow silicon onto an insulating substrate – your basic silicon-on-insulator (SOI) configuration – and if your implants go all the way through the silicon to the insulator, the body is simply that portion of the silicon between the source and drain. And because the body isn’t connected to the bulk of the wafer – the bulk is an insulator – it’s not connected to anything (unless you specifically add a contact for it). That is, the body is “floating” – generally a bad thing.

But if the body is floating, then if charge is somehow deposited in there and the depositing mechanism is removed so that the body is isolated, then the charge has nowhere to go and you end up with a storage mechanism. The questions are, how can you exploit that charge and how can you deposit the charge?

The obvious way to try to make use of the charge is to have it participate in the turn-on characteristics of the MOS transistor. If you can somehow monkey with the threshold, then maybe you can detect the presence of the charge. Problem is, MOS thresholds are a very sensitive thing, and this is a very subtle effect. Creating an array of millions and billions of transistors with thresholds all within microvolts of each other is a dicey proposition.

Innovative Silicon took things in a different direction by realizing that the combination of, say, an N source, a P body, and an N drain make more than just an N-channel transistor. They also make an NPN bipolar transistor, where the body forms the base of the transistor. This transistor is always there but is considered a parasite and a nuisance – especially with a floating base. But no longer.

The turn-on voltage of a bipolar transistor is much more stable than the threshold of an MOS transistor. It’s much more of a physical constant, and therefore billions of bipolar transistors are much more likely to have well-aligned turn-on characteristics. Using this bipolar transistor provides an opportunity to detect the presence of charge in the body.

Let’s say you somehow managed to stash a bunch of holes in the body of some transistors (more on that in a minute), but not others, and then you wanted to detect which ones had the charge. If those holes were up against the gate of the N-channel, and then the gate was raised to a voltage just under the NPN turn-on voltage (and below the MOS threshold), the gate – which is a capacitor – would couple the top of the body (which is the base of the NPN) up as well.

Those transistors that had the extra holes in the body right up by the gate would have just a bit extra potential in the body, which would push the body voltage just over the NPN turn-on when pumped up by the gate. Those transistors without extra holes would be pumped up only to the gate voltage – just below the NPN turn-on – because they don’t have the extra potential of the added holes, so the NPN would not turn on. Only those transistors with extra holes would have the NPN turn on, and the resulting current would be your indicator that there was extra charge in the body.

So that answers the first question. The second question was how you get the charges there in the first place. And here they rely on an effect that would presumably be second-order at best under normal circumstances. As a current flows in the channel (now think N-channel), the electrons bump into atoms along the way or, more precisely, bump into electrons around atoms along the way, and they can knock those electrons out of the atomic shell. If the electron gets swept away in the current, you’re left with excess holes: this is called “impact ionization.”

Now, if you’re like me, you ask the question, “Why aren’t these holes immediately filled by all these electrons that are zooming around?” And someone like Innovative Silicon’s Dr. Wayne Ellis will patiently remind you that the reason there is an N channel in the first place is that the region has been depleted of holes. And that’s because of the gate voltage, which repels holes and attracts electrons. That same field will tend to push most of the newly-created holes into the body, away from the surplus of electrons. (Yes, at the detailed level, there are other possible fates for a very few of the holes; we’ll leave that as an exercise for the reader.)

As more of these excess holes get pushed into the body, the body potential starts to rise, and, at some point, the NPN can turn on. Note that this would never happen in a standard silicon wafer, because the body (or base of the NPN) would be grounded or pinned to some other voltage that would keep the NPN from ever turning on. It’s the fact that the body is floating that allows this to occur.

Once the NPN is turned on, you get even more current, since the current isn’t limited just to the channel anymore. This creates more holes and helps build this positive surplus. If you then, without advance notice, shut everything down – lower the gate, ground the source and drain, you’ll get a little more current as some of the holes dissipate, but once the body voltage has dropped below the NPN turn-on, the NPN shuts off, and you no longer have any current flowing. The holes that remain in the body are stuck there. And, in fact, by grounding the gate, you can attract the holes up to the channel region of the body.

Now, to read the cell, you can do the gate-voltage-bumping thing, and, if the excess charge is present, the NPN will turn on, causing current to flow. The really cool thing is that this read current starts to create more holes again, so the read operation is self-reinforcing, not destructive. No refresh is required after a read.

What if you want to write the opposite value to that cell once the excess holes are there? It’s easy: turn on the MOS transistor gate while grounding the source and drain. The excess positive charge will dissipate away.

Does this work in real life? And in full production? Reliably enough to become a business? Well, clearly Innovative Silicon thinks it will. They have also convinced, to date, AMD and Hynix that it has promise. AMD has licensed it as an embedded cell within their processors for use on an existing (and hopefully minimally modified) process; Hynix would use it for stand-alone memory and therefore would be free to do more to optimize the process. Innovative Silicon doesn’t currently plan to sell chips themselves; they’re licensing only, with a focus on integrated device manufacturers (IDMs, i.e., dudes with fabs). With particular focus on the stand-alone memory side of things. The proof of the pudding won’t come for a while; this is a two- to three-year process bring-up, according to Innovative Silicon’s Jeff Lewis. Not something that is, presumably, taken on lightly.

But then again, as MOSAID’s Dick Foss said at this year’s International SoC Conference, “The one thing about emerging memories is that they never emerge.” Innovative Silicon has some time to prove him right or wrong.